Sources for Additiona l Information. Emulator Pin Descriptions (Continued). Clock Signals. Mechanism for booting on the ADSP-2192, страница 10

Powerdown C ontrol

The ADSP-2192 supports two states with distinct power management and functionality capabilities. These states are referred to as Platform States and are denoted PS0 and PS1.

These platform states encompass both hardware and software states. The driver and DSP code take responsibility for detailed power management, and minimum power levels are achieved regardless of OS or BIOS. The driver and DSPs manage power by changing platform states as necessary in response to events. Such events may include changes in the function’s PCI/USB power management D-state or PME_Enable state (set via the external PME pin), or external wakeup events detected on the external dedicated general-purpose flag pins (IO0-7). See Table B-5 on page B-18 for more information about the PME bit.

The PS0 platform state indicates that the platform is running and is operational. The power state is D0 and the chip is at full power.

The PS1 platform state indicates that the platform is shut down and is in the lowest power state. The power state may be D0, D3, or D3cold. The DSPs are powered down, the AC’97 is shut down, and XTAL and the clocks to the DSPs are stopped. No wakeup is enabled, and any enabled wake events signal PME directly without DSP intervention.

Entering a nd Exiting Powerdo wn

Each of the DSPs on the ADSP-2192 has a register to control powerdown and powerup functions. These registers are PWRP1 (the DSP1 Interrupt/Powerdown Register) and PWRP2 (the DSP2 Interrupt/Powerdown Register).

To power down one of the DSPs, write a 1 to the PD (power down) control bit of that DSP’s Interrupt/Powerdown Register. Writing a 1 causes the DSP to enter its powerdown handler. The same process can be used to abort a powerup; if the DSP is in the powerdown handler after executing an IDLE, writing a 1 causes the DSP to re-enter the powerdown handler immediately after executing the RTI.

To power up one of the DSPs, write a 1 to the PU (power up) control bit of that DSP’s Interrupt/Powerdown Register. Writing a 1 causes the DSP to exit the IDLE within its powerdown handler, effectively powering up. The same process can also be used to abort a powerdown. If the DSP is in the powerdown handler prior to the IDLE, writing a 1 causes execution to continue immediately through the IDLE without stopping the clocks.

The current value of the PD and PU control bits indicate the current state of the DSP. If PD=1, this DSP is powered down; either it is in the powerdown handler and has executed an IDLE instruction, or the DSP Clock Generator (PLL) is not running and stable. If PU=1, this DSP is in the powerdown interrupt handler, whether or not it has executed the powerdown IDLE.

If both DSPs are powered down, the DSP clock generator is also powered down; the DSP clock generator restarts automatically when either DSP wakes up. DSP memory cannot be accessed via PCI when the DSP clock generator is powered down, and memory reads must not be performed while the DSPs are powering up.

While the processor is in the powerdown mode, the processor is in CMOS standby. This feature allows the lowest level of power consumption where most input pins are ignored. Active inputs need to be held at CMOS levels to achieve lowest power. More information can be found in the section “Processor Operation During Powerdown” on page 11-36.

Powering Down the USB

The ADSP-2192 can be powered down through the USB interface. To do this, the software driver sends USB REGWR commands. The USB REGWR command comes down on the control pipe (Endpoin t0) and writes the appropriate bits to registers PWRP1 (DSP 1 Interrupt/Powerdown Register at Page 0x00, Address 0x08) and PWRP2 (DSP 2 Interrupt/Powerdown Register at Page 0x00, Address 0x0A).

Once these bits have been written to the PWRP1 and PWRP2 registers, the

DSPs park in their idle states. If a full USB powerdown is desired, the