Sources for Additiona l Information. Emulator Pin Descriptions (Continued). Clock Signals. Mechanism for booting on the ADSP-2192, страница 5

•  Reads data from the serial EEPROM if appropriate

•  Sets up bus configurations

•  Transfers control to PCI or USB

At this point the loader kernel enters into an infinite loop, waiting for instructions. Once the PCI or USB device has completed booting the DSP, the device can write an instruction to a pre-defined location

(0x000000 in Data Memory), at which point the DSP will execute any one of a list of supported commands. These supported commands include the following:

•  Jump to program memory without returning (to leave the loader kernel and begin user code)

•  Read a word from EEPROM

•  Enable write mode on EEPROM

•  Write a word to EEPROM

•  Re-read patch block from EEPROM (if bus configuration may have overwritten locations)

•  Enter power-down state

You can also write code to perform these operations during runtime by writing the appropriate value into the pre-defined memory address and then by performing a CALL to address 0x014F00 (a location in the ROM). The loader kernel performs the requested command and then returns control to the user code.

Table 11-9 shows the values and descriptions for the supported functions. For commands that require multiple arguments, the arguments are placed in Data Memory addresses 0x0001, 0x0002, and 0x0003 respectively.

Table 11-9. User-Defined Loader Kernel Function Values

Resets a nd Softwa re-Forc ed Rebooting

Table 11-10 on page 11-17 shows the state of the processor registers after a reset or a software-forced reboot. The values of any registers not listed are unchanged by a reset or a reboot. The contents of on-chip memory are unchanged after PORST, except for the data-memory-mapped control/status registers, as shown in Table 11-10.

During booting (and rebooting), all interrupts are masked, and autobuffering is disabled. The timers run during a reboot. If a timer interrupt occurs during the reboot, it is masked. Thus, if more than one timer interrupt occurs during the reboot, the processor latches only the first, and a timer overrun can occur.

Table 11-10. ADSP-2192 Register State after Reset or Software Reboot