Sources for Additiona l Information. Emulator Pin Descriptions (Continued). Clock Signals. Mechanism for booting on the ADSP-2192, страница 4

Multifunction operations available on the ADSP-2192 include:

•  ALU/MAC with DM and PM dual read using DAGS 1and2 post-modify

•  Multifunction ALU/MAC with DM/PM read or write using DAG post-modify

•  ALU/MAC/Shift and any DREG-to-DREG transfer

•  Conditional ALU/MAC/Shift

•  Unconditional Register File ALU/MAC

Ma xim izing Pe rform a nc e of DSP A lg orithm s

Table 11-8 lists the registers available for multifunction instructions.

Table 11-8. Available Registers for Multifunction Instructions

Operation	Available XOPs	Available YOPs
ALU	AX0, AX1, AR, MR0, MR1, MR2, SR0, SR1	AY0, AY1, AF, the value zero
MAC	MX0, MX1, AR, MR0, MR1, MR2, SR0, SR1	MY0, MY1, SR1, the value zero
Shifts	SI, SR0, SR1, SR2, AR, AX0, AX1, AY0, AY1, MX0, MX1 MY0, MY1, MR0, MR1, MR2	N/A

For more information about these performance enhancements and instructions for optimizing the code in your DSP algorithms, see Application Note EE-122, available from the ADSP-2192 product page on the www.analog.com web site.

Re se tting the Proc e ssor

The ADSP-2192 supports booting via either the PCI interface or the USB interface. The boot loader kernel, located in the DSP ROM, determines how the DSP boots (PCI or USB). The kernel then sets up and initializes appropriate DSP registers to facilitate the booting.

Three methods for resetting the processor on the ADSP-2192 are discussed in this section: Power On Reset, Forced Reset Via PCI/USB, and Software Reset. The reset type is specified by bits 8 and 9 (CRST<1:0>) of the Chip Mode/Status Register (CMSR), as follows:

•  CRST<1:0>=00—Power On Reset

•  CRST<1:0>=01—(Reserved)

•  CRST<1:0>=10—PCI/USB Hard Reset

•  CRST<1:0>=11—Soft Reset from CMSR RST bit.

For information about resetting the AC’97 link, refer to “Resetting the AC’97” on page 9-12.

Power O n Reset

The ADSP-2192 has an internal Power On Reset circuit that resets the DSP when power is applied. A Power On Reset (PORST) signal can also initiate this master reset. When the Power On Reset is invoked, program flow jumps to the first location of the loader kernel at address 0x14000 and begins execution.

Forc ed Reset Via PC I/USB

In addition to the Power On Reset (PORST), the ADSP-2192 can also be reset by the PCI or USB interfaces. These interfaces reset the DSP under their control as needed. A reset via the PCI or USB device causes program flow to jump to the command monitor that is part of the loader kernel, bypassing the serial EEPROM detection/reading subroutines.

For more information about resets via PCI or USB, see “Resets” on page 8-14.

Software Reset

The DSP can generate a software reset by using theRSTD bit in the DSP Interrupt/Powerdown Registers. (See “ADSP-2192 DSP Peripheral Registers” on page B-1 for more information about the RSTD bit.) Generally, reset conditions are handled by forcing the DSPs to execute ROM- or RAM-based Reset Handler code. The Reset Handler to be executed can be dictated by the Reset Source as defined by the CRST[1:0] bits in the Chip Mode/Status Register (CMSR). If not otherwise defined, the loader kernel jumps to the first location of internal PM memory at address 0x10000 and commences execution.

The exact Reset Functionality is therefore defined by the ROM and RAM Reset Handler Code and as such is programmable.

Reset Prog ression

Once a reset has occurred and the loader kernel begins running, it does the following:

•  Determines the type of reset (Power On Reset, PCI/USB Reset, or Software Reset),

•  Configures interrupts