Sources for Additiona l Information. Emulator Pin Descriptions (Continued). Clock Signals. Mechanism for booting on the ADSP-2192, страница 13

At powerup, deasserting ACRST from the cold state causes the BITCLK master to start, but the controller does not necessarily start generating SYNC pulses until it is enabled. The state in which BITCLK is running but SYNC is halted is called IDLE.

When powered down, a wakeup protocol is defined using the SDI pins. Wakeups are signalled using SDI Slot 12 Bit 0 during the running state; wakeups are signalled using a high level on SDI during all other states. If it is enabled to do so, the controller can restart the link upon receiving this wakeup signal.

For more information about AC’97 power modes, refer to “AC’97 Codec Port” on page 9-1.

Using Powerdown as A Non-Maskable Interrupt

The powerdown interrupt is never masked, although it can be disabled with the DIS INTS instruction. It is possible to use this interrupt for other purposes if desired. The processor does not go into powerdown until an IDLE instruction is executed. If an RTI is executed before the IDLE instruction, then the processor returns from the powerdown interrupt and the powerdown sequence is aborted.

It is possible to place a series of instructions at the powerdown interrupt vector location 0x002C. This routine should end with an RTI instruction and should not contain an IDLE instruction if the interrupt is to be used for purposes other than powerdown.

Em ula tion

Analog Devices DSP emulators use the JTAG test access port of the ADSP-2192 processor to monitor and control the target board processor during emulation. The emulator provides full-speed emulation, allowing inspection and modification of memory, registers, and processor stacks. Non-intrusive in-circuit emulation is assured by the use of the processor’s JTAG interface; the emulator does not affect target system loading or timing.

Note that the ADSP-2192 JTAG port does not support boundary scan.

For more information about JTAG emulation, see the “JTAG Test-Emulation Port” on page 10-1.