Создание структурных и поведенческих моделей исследуемого цифрового узла (элемент К555ИМ3 (полный двоичный четырехразрядный сумматор)) в пакетах OrCAD 9.1, Active-HDL 8.1, страница 10

+          D0_GATE IO_LS IO_LEVEL={IO_LEVEL}

U1 or(2) DPWR DGND

+          A_BUF B_BUF   C

+          D_LP5_1 IO_LS MNTYMXDLY={MNTYMXDLY}

U2 nand(2) DPWR DGND

+          A_BUF B_BUF   D

+          D_LP5_2 IO_LS MNTYMXDLY={MNTYMXDLY}

U3 and(2) DPWR DGND

+          C D   Y

+          D_LP5_2 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.ends

.model D_LP5_1 ugate (

+          tplhty=0ns      tplhmx=12ns

+       tphlmx=12ns

+          )

.model D_LP5_2 ugate (

+          tplhty=20ns    tplhmx=12ns

+          tphlty=3ns      tphlmx=12ns

+          )

.model D_LP5_3 ugate (

+          tplhty=12ns    tplhmx=0ns

+          )

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Приложение 2. VHDL-модели отечественных элементов.

---------------------------------------------------/INV/--------------------------------------------------------------------

LIBRARY ieee;                        

USE ieee.std_logic_1164.all;

ENTITY K555LN1 IS PORT(

A : IN  std_logic;

Y : OUT  std_logic);

END K555LN1;    

ARCHITECTURE model OF K555LN1 IS

BEGIN

    Y <= not A; 

END model;

-------------------------------------------------/NOR2/-------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY K555LE1 IS PORT(

A : IN  std_logic;

B : IN  std_logic;

Y : OUT  std_logic);

END K555LE1;

ARCHITECTURE model OF K555LE1 IS

    BEGIN

    Y <= NOT ( A OR B );

END model;

------------------------------------------------/NOR3/-------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY K555LE4 IS PORT(

A : IN  std_logic;

B : IN  std_logic;

C : IN  std_logic;

Y : OUT  std_logic);

END K555LE4;

ARCHITECTURE model OF K555LE4 IS

    BEGIN

    Y <= NOT ( A OR B OR C );

    END model;

-------------------------------------------------/AND2/-------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY K555LI1 IS PORT(

A : IN  std_logic;

B : IN  std_logic;

Y : OUT  std_logic);

END K555LI1;

ARCHITECTURE model OF K555LI1 IS

    BEGIN

    Y <=  ( A AND B );

END model;

-------------------------------------------------/AND3/-------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY K555LI3 IS PORT(

A : IN  std_logic;

B : IN  std_logic;

C : IN  std_logic;

Y : OUT  std_logic);

END K555LI3;

ARCHITECTURE model OF K555LI3 IS

    BEGIN

    Y <=  ( A AND B AND C );

    END model;

----------------------------------------------------/XOR2/----------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY K555LP5 IS PORT(

A : IN  std_logic;

B : IN  std_logic;

Y : OUT  std_logic);

END K555LP5;

ARCHITECTURE model OF K555LP5 IS

    BEGIN

    Y <=  ( A XOR B ) after 24ns;

    END model;

-------------------------------------------------/AND2/-------------------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY K555LI1A IS PORT(

A : IN  std_logic;

B : IN  std_logic;

Y : OUT  std_logic);

END K555LI1A;

ARCHITECTURE model OF K555LI1A IS

    BEGIN

    Y <=  ( A AND B ) after 17ns;

END model;

-------------------------------------------------------/NAND2/---------------------------------------------------------

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY K555LA3 IS PORT(

A : IN  std_logic;

B : IN  std_logic;

Y : OUT  std_logic);

END K555LA3;

ARCHITECTURE model OF K555LA3 IS

    BEGIN

    Y <= NOT ( A AND B );

    END model;

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