Разработка цифрового узла, создание его структурных и поведенческих моделей (на языках SPICE, DSL, VHDL, в пакетах DesignLab 8, OrCAD 9.1, Active-HDL 6.2), страница 11

--входов (в противофазе), то изменение сигнала на выходе должно произойти через 12нс:

                     if (Y_INT_NEW(0)='1' and Y_INT_PREV(0)='0' and ((I1='0' and I1'event) or (I2='0' and I2'event) or (I3='0' and I3'event) or (I4='0'  and I4'event) or (I5='0'  and I5'event) or (I6='0'  and I6'event) or (I7='0'  and I7'event) or (I8='0'  and I8'event) or (I9='0' and I9'event)))

                                   then Y0<=Y_INT_NEW(0)  after 21 ns;

--иначе если выход Y0 переключился с 1 на 0 вследствие прихода активного уровня на какой--- либо из входов (в противофазе), то изменение сигнала на выходе должно произойти через     --15нс:

     elsif (Y_INT_NEW(0)='0' and Y_INT_PREV(0)='1' and ((I1='1' and I1'event) or (I2='1' and I2'event) or (I3='1' and I3'event) or (I4='1'  and I4'event) or (I5='1'  and I5'event) or (I6='1'  and I6'event) or (I7='1'  and I7'event) or (I8='1'  and I8'event) or (I9='1' and I9'event)))

                     then Y0<=Y_INT_NEW(0)  after 15 ns;

--если предыдущие два условия не выполнились, значит выходной сигнал переключился

--относительно входного в фазе – задержка 12 нс:

        else

                     Y0<=Y_INT_NEW(0) after 12 ns;

        end if;  

--для остальных выходов - аналогично

--выход Y1

                     if (Y_INT_NEW(1)='1' and Y_INT_PREV(1)='0' and ((I1='0' and I1'event) or (I2='0' and I2'event) or (I3='0' and I3'event) or (I4='0'  and I4'event) or (I5='0'  and I5'event) or (I6='0'  and I6'event) or (I7='0'  and I7'event) or (I8='0'  and I8'event) or (I9='0' and I9'event)))

                                   then Y1<=Y_INT_NEW(1)  after 21 ns;

        elsif (Y_INT_NEW(1)='0' and Y_INT_PREV(1)='1' and ((I1='1' and I1'event) or (I2='1' and I2'event) or (I3='1' and I3'event) or (I4='1'  and I4'event) or (I5='1'  and I5'event) or (I6='1'  and I6'event) or (I7='1'  and I7'event) or (I8='1'  and I8'event) or (I9='1' and I9'event)))

                     then Y1<=Y_INT_NEW(1)  after 15 ns;

        else

                     Y1<=Y_INT_NEW(1) after 12 ns;

        end if;  

--выход Y2

                     if (Y_INT_NEW(2)='1' and Y_INT_PREV(2)='0' and ((I1='0' and I1'event) or (I2='0' and I2'event) or (I3='0' and I3'event) or (I4='0'  and I4'event) or (I5='0'  and I5'event) or (I6='0'  and I6'event) or (I7='0'  and I7'event) or (I8='0'  and I8'event) or (I9='0' and I9'event)))

                                   then Y2<=Y_INT_NEW(2)  after 21 ns;

        elsif (Y_INT_NEW(2)='0' and Y_INT_PREV(2)='1' and ((I1='1' and I1'event) or (I2='1' and I2'event) or (I3='1' and I3'event) or (I4='1'  and I4'event) or (I5='1'  and I5'event) or (I6='1'  and I6'event) or (I7='1'  and I7'event) or (I8='1'  and I8'event) or (I9='1' and I9'event)))

                     then Y2<=Y_INT_NEW(2)  after 15 ns;

        else

                     Y2<=Y_INT_NEW(2) after 12 ns;

        end if;  

--выход Y3

                     if (Y_INT_NEW(3)='1' and Y_INT_PREV(3)='0' and ((I1='0' and I1'event) or (I2='0' and I2'event) or (I3='0' and I3'event) or (I4='0'  and I4'event) or (I5='0'  and I5'event) or (I6='0'  and I6'event) or (I7='0'  and I7'event) or (I8='0'  and I8'event) or (I9='0' and I9'event)))

                                   then Y3<=Y_INT_NEW(3)  after 21 ns;

        elsif (Y_INT_NEW(3)='0' and Y_INT_PREV(3)='1' and ((I1='1' and I1'event) or (I2='1' and I2'event) or (I3='1' and I3'event) or (I4='1'  and I4'event) or (I5='1'  and I5'event) or (I6='1'  and I6'event) or (I7='1'  and I7'event) or (I8='1'  and I8'event) or (I9='1' and I9'event)))

                     then Y3<=Y_INT_NEW(3)  after 15 ns;

        else

                     Y3<=Y_INT_NEW(3) after 12 ns;

        end if;                                 

       end process;

END BEHAVIOR;