Проектирование специализированного микроконтроллера, реализующего полнофункциональную RSA схему шифрования, страница 20

);

end lfsr_512;

architecture behavioral of lfsr_512 is

component dff_1 is

port(clk : in std_logic;

     en  : in std_logic;

     reset_l : in std_logic;

     seed    : in std_logic;

     d   : in std_logic;

     q   : out  std_logic);

end component;

signal q_i : std_logic_vector(520 downto 0);

signal d_i : std_logic;

signal seed_i : std_logic_vector(520 downto 0);

begin

seed_i <= seed & "101010101";

output <= q_i(511 downto 0);

d_i <= q_i(520) xor q_i(488);

my_dff_520 : dff_1 port map(clk, ce, reset_l, seed_i(520), d_i, q_i(520));

lfsr: for i in 519 downto 0 generate

      my_dff: dff_1 port map(clk, ce, reset_l, seed_i(i), q_i(i+1), q_i(i));  

end generate;

end architecture;

Текст файла « prime_rom.vhd» :

----------------------------------------------------------------------

-- This file is owned and controlled by Xilinx and must be used     --

-- solely for design, simulation, implementation and creation of    --

-- design files limited to Xilinx devices or technologies. Use      --

-- with non-Xilinx devices or technologies is expressly prohibited  --

-- and immediately terminates your license.                         --

--                                                                  --

-- Xilinx products are not intended for use in life support         --

-- appliances, devices, or systems. Use in such applications are    --

-- expressly prohibited.                                            --

--                                                                  --

-- Copyright (C) 2001, Xilinx, Inc.  All Rights Reserved.           --

----------------------------------------------------------------------

-- You must compile the wrapper file prime_rom.vhd when simulating

-- the core, prime_rom. When compiling the wrapper file, be sure to

-- reference the XilinxCoreLib VHDL simulation library. For detailed

-- instructions, please refer to the "Coregen Users Guide".

 

-- The synopsys directives "translate_off/translate_on" specified

-- below are supported by XST, FPGA Express, Exemplar and Synplicity

-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;

ENTITY prime_rom IS

    port (

    addr: IN std_logic_VECTOR(8 downto 0);

    clk: IN std_logic;

    dout: OUT std_logic_VECTOR(11 downto 0);

    en: IN std_logic);

END prime_rom;

ARCHITECTURE prime_rom_a OF prime_rom IS

component wrapped_prime_rom

    port (

    addr: IN std_logic_VECTOR(8 downto 0);

    clk: IN std_logic;

    dout: OUT std_logic_VECTOR(11 downto 0);

    en: IN std_logic);

end component;

-- Configuration specification

    for all : wrapped_prime_rom use entity XilinxCoreLib.blkmemsp_v4_0(behavioral)

               generic map(

                              c_reg_inputs => 0,

                              c_addr_width => 9,

                              c_has_sinit => 0,

                              c_ysinit_is_high => 1,

                              c_has_rdy => 0,

                              c_width => 12,

                              c_has_en => 1,

                              c_ymake_bmm => 0,

                              c_yen_is_high => 1,

                              c_yprimitive_type => "4kx1",

                              c_yhierarchy => "hierarchy1",

                              c_mem_init_file => "prime_rom.mif",

                              c_ywe_is_high => 1,

                              c_yuse_single_primitive => 0,

                              c_depth => 512,

                              c_has_nd => 0,

                              c_has_default_data => 0,

                              c_default_data => "0",

                              c_ytop_addr => "1024",

                              c_limit_data_pitch => 8,

                              c_pipe_stages => 0,

                              c_ybottom_addr => "0",