nxstate <= fetch_prime_1;
end if;
when fetch_prime_1 => if empty = '0' then
nxstate <= get_prime_1;
end if;
when get_prime_1 => if rd_ack = '1' then
nxstate <= fetch_prime_2;
end if;
when fetch_prime_2 => if empty = '0' then
nxstate <= get_prime_2;
end if;
when get_prime_2 => if rd_ack = '1' then
nxstate <= mult1;
end if;
when mult1 => if m_valid_i = '1' then
nxstate <= mult2;
end if;
when mult2 => if m_valid_i = '1' then
nxstate <= idle;
end if;
when others => nxstate <= idle;
end case;
end process prime_test_fsm;
process(clk)
begin
if clk'event and clk = '1' then
if reset_l_1 = '0' then
fi_out <= (others => '0');
n_out <= (others => '0');
ready <= '0';
out_valid <= '0';
a_i <= (others => '0');
b_i <= (others => '0');
mul_start <= '0';
rd_en <= '0';
else
ready <= '0';
out_valid <= '0';
mul_start <= '0';
rd_en <= '0';
case state is
when idle => ready <= '1';
if reset_l_1 = '1' and start = '1' then
ready <= '0';
end if;
when fetch_prime_1 => if empty = '0' then
rd_en <= '1';
end if;
when get_prime_1 => if rd_ack = '1' then
rd_en <= '1';
a_i <= c & prime_in;
end if;
when fetch_prime_2 => if empty = '0' then
rd_en <= '1';
end if;
when get_prime_2 => if rd_ack = '1' then
b_i <= c & prime_in;
end if;
when mult1 => if mul_ready = '1' then
mul_start <= '1';
end if;
if m_valid_i = '1' then
n_out <= m_i;
end if;
when mult2 => if mul_ready = '1' then
mul_start <= '1';
a_i <= a_i(1023 downto 1) & '0';
b_i <= b_i(1023 downto 1) & '0';
end if;
if m_valid_i = '1' then
fi_out <= m_i;
out_valid <= '1';
end if;
when others => null;
end case;
end if;
end if;
end process;
end architecture;
Текст файла «mod_exp_1024.vhd» :
-- Modular Exponentiation
-- e = a^b mod n
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity mod_exp_1024 is
port (
clk : in std_logic;
reset_l : in std_logic;
start : in std_logic;
ready : out std_logic;
A: IN std_logic_VECTOR(1023 downto 0);
B: IN std_logic_VECTOR(1023 downto 0);
N: in std_logic_vector(1023 downto 0);
E_valid : out std_logic;
E: OUT std_logic_VECTOR(1023 downto 0));
end mod_exp_1024;
architecture my_mod_exp of mod_exp_1024 is
component mod_mult_1024
port (
clk : in std_logic;
reset_l : in std_logic;
start : in std_logic;
ready : out std_logic;
A: IN std_logic_VECTOR(1023 downto 0);
B: IN std_logic_VECTOR(1023 downto 0);
N: IN std_logic_VECTOR(1023 downto 0);
M_valid : out std_logic;
M: OUT std_logic_VECTOR(1023 downto 0));
end component;
signal a_i,b_i,m_i: std_logic_vector(1023 downto 0);
signal mult_ready, mult_start, m_valid_i : std_logic;
signal k : integer;
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