Проектирование специализированного микроконтроллера, реализующего полнофункциональную RSA схему шифрования, страница 13

                       b2(0) <= '1';

                       rd_en <= '1';

                     end if;

        when fetch_b => addr <= addr + 1;

 

        when get_b => b_buf <= data;

        when div_1 =>  if div_ready_i = '1' then

                       div_start_i <= '1';

                     end if;  

                     if d_valid_i = '1' then

                       q <= d_i;

                       b3 <= r_i;

                       a3 <= b3;

                     end if;

        when mul => if mul_ready_i = '1' then

                      mul_start_i <= '1';

                    end if;

                    if m_valid_i = '1' then

                      m_buf <= m_i;

                    end if;

        when add => if add_ready_i = '1' then

                      add_start_i <= '1';

                    end if;

                    if s_valid_i = '1' then

                      b2 <= s_i;

                      a2 <= b2;

                      q_tmp <= (others => '0');

                    end if;

        when test => if b3 = x"000" then

                       rd_en <= '1';

                       a2 <= (others => '0');

                       b2 <= (others => '0');

                       b2(0) <= '1';

                     end if;

        when div_2 => if a3 >= b3 then

                        q_tmp <= q_tmp + 1;

                        a3 <= a3 - b3;

                      else

                        b3 <= a3;

                        a3 <= b3;

                      end if;

        when output => out_valid <= '1';

                       d <= b2;

                       e(1023 downto 12) <= (others => '0');

                       e(11 downto 0) <= b_buf;

        when others => null;

      end case;

    end if;

  end if;

end process;

end architecture;

Текст файла « gen_n.vhd» :

-- Generate n = p*q

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

 

entity gen_n is

  port (

        clk : in std_logic;

        reset_l : in std_logic;

        start : in std_logic;

        ready : out std_logic;

        prime_in: IN std_logic_VECTOR(511 downto 0);

    empty : in std_logic;

        rd_ack : in std_logic;

        rd_en : out std_logic;

        out_valid : out std_logic;

        fi_out : out std_logic_vector(1023 downto 0);

        n_out: OUT std_logic_VECTOR(1023 downto 0));

end gen_n;

architecture my_gen_n of gen_n is

component mult_1024

        port (

        clk : in std_logic;

        reset_l : in std_logic;

        start : in std_logic;

        ready : out std_logic;

        A: IN std_logic_VECTOR(1023 downto 0);

        B: IN std_logic_VECTOR(1023 downto 0);

        m_valid : out std_logic;

        m: OUT std_logic_VECTOR(1023 downto 0));

end component;

signal a_i, b_i, m_i : std_logic_vector(1023 downto 0);

signal mul_ready : std_logic;

signal mul_start : std_logic;

signal m_valid_i : std_logic;

signal start_i : std_logic;

signal reset_l_1 : std_logic;

constant c : std_logic_vector(511 downto 0) := (others => '0');

type gen_n_state is (idle, fetch_prime_1, get_prime_1, fetch_prime_2, get_prime_2, mult1, mult2);

signal state, nxstate : gen_n_state;

begin

my_mult_1024 : mult_1024

   port map (

             clk => clk,

             reset_l => reset_l_1,

             start => mul_start,

             ready => mul_ready,

             A => a_i,

             B => b_i,

             m_valid => m_valid_i,

             m => m_i);

process(clk)

begin

  if clk'event and clk = '1' then

    reset_l_1 <= reset_l;

  end if;

end process;

process(clk)

begin

  if clk'event and clk = '1' then

    if reset_l_1 = '0' then

      state <= idle;

    else

      state <= nxstate;

    end if;

  end if;

end process;

prime_test_fsm: process(state, reset_l_1, start, start_i, empty, rd_ack, prime_in, m_valid_i)

begin

  nxstate <= state;

  case state is

    when idle => if reset_l_1 = '1' and start = '1' then