mod_mult_fsm: process(k, j, state, reset_l_1, start, s_valid_i, b_buf, b_buf_tmp)
begin
nxstate <= state;
case state is
when idle => if reset_l_1 = '1' and start = '1' then
nxstate <= cal_k;
end if;
when cal_k => if k /= 0 then
if b_buf_tmp(1023) = '1' then
if b_buf(0) = '1' then
nxstate <= add1;
else
nxstate <= shift;
end if;
end if;
else
nxstate <= output;
end if;
when add1 => if s_valid_i = '1'then
nxstate <= shift;
end if;
when shift => nxstate <= inc_j;
when inc_j => if j = k then
nxstate <= output;
elsif b_buf_tmp(0) = '0' then
nxstate <= shift;
else
nxstate <= add1;
end if;
when output => nxstate <= idle;
when others => nxstate <= idle;
end case;
end process mod_mult_fsm;
process(clk)
begin
if clk'event and clk = '1' then
if reset_l_1 = '0' then
m <= (others => '0');
ready <= '0';
m_valid <= '0';
a_i <= (others => '0');
b_i <= (others => '0');
c_in_i <= '0';
add_i <= '1';
add_start <= '0';
k <= 1024;
j <= 1;
b_buf_tmp <= (others => '0');
a_exp <= (others => '0');
a_buf <= (others => '0');
b_buf <= (others => '0');
m_buf <= (others => '0');
c_out_buf <= '0';
else
ready <= '0';
m_valid <= '0';
a_i <= (others => '0');
b_i <= (others => '0');
c_in_i <= '0';
add_start <= '0';
case state is
when idle => k <= 1024;
j <= 1;
ready <= '1';
m <= (others => '0');
b_buf_tmp <= (others => '0');
a_exp <= (others => '0');
a_buf <= (others => '0');
b_buf <= (others => '0');
m_buf <= (others => '0');
c_out_buf <= '0';
if reset_l_1 = '1' and start = '1' then
ready <= '0';
a_buf <= a;
b_buf <= b;
b_buf_tmp <= b;
a_exp <= a;
end if;
when cal_k => if b_buf_tmp(1023) = '0' then
k <= k - 1;
b_buf_tmp <= b_buf_tmp(1022 downto 0) & '0';
else
b_buf_tmp <= '0' & b_buf(1023 downto 1);
end if;
when add1 => if add_ready = '1' then
add_start <= '1';
add_i <= '1';
a_i <= a_exp;
b_i <= m_buf;
c_in_i <= '0';
end if;
if s_valid_i = '1' then
m_buf <= s_i;
end if;
when shift => a_exp <= a_exp(1022 downto 0) & '0';
when inc_j => j <= j + 1;
b_buf_tmp <= '0' & b_buf_tmp(1023 downto 1);
when output => m_valid <= '1';
m <= m_buf;
when others => null;
end case;
end if;
end if;
end process;
end architecture;
Текст файла « lfsr_512» :
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
entity lfsr_512 is
port(
clk : in std_logic;
ce : in std_logic;
reset_l: in std_logic;
seed : in std_logic_vector(511 downto 0);
output : out std_logic_vector(511 downto 0)
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