Проектирование специализированного микроконтроллера, реализующего полнофункциональную RSA схему шифрования, страница 16

                        if b_buf(1023) = '0' then

                          k <= k - 1;

                          b_buf <= b_buf(1022 downto 0) & '0';

                        end if;

                      end if;

        when output => e <= e_buf;

                       e_valid <= '1';

        when others => null;

      end case;

    end if;

  end if;

end process;

end architecture;

Текст файла « mod_mult_1024.vhd» :

-- Modular Multiplication

-- m = a*b mod n

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity mod_mult_1024 is

  port (

        clk : in std_logic;

        reset_l : in std_logic;

        start : in std_logic;

        ready : out std_logic;

        A: IN std_logic_VECTOR(1023 downto 0);

        B: IN std_logic_VECTOR(1023 downto 0);

        N: in std_logic_vector(1023 downto 0);

        M_valid : out std_logic;

        M: OUT std_logic_VECTOR(1023 downto 0));

end mod_mult_1024;

architecture my_mod_mult of mod_mult_1024 is

component add_sub_1024

        port (

        clk : in std_logic;

        reset_l : in std_logic;

        start : in std_logic;

        ready : out std_logic;

        A: IN std_logic_VECTOR(1023 downto 0);

        B: IN std_logic_VECTOR(1023 downto 0);

        C_IN: IN std_logic;

        C_OUT: OUT std_logic;

        ADD: IN std_logic;

        s_valid : out std_logic;

        S: OUT std_logic_VECTOR(1023 downto 0));

end component;

signal a_i,b_i_1, b_i_2, s_i_1, s_i_2 : std_logic_vector(1023 downto 0);

signal add_ready_1, add_ready_2, add_start_1, add_start_2 : std_logic;

signal s_valid_i_1, s_valid_i_2 : std_logic;

signal c_out_i_1, c_out_i_2 : std_logic;

signal add_i : std_logic;

signal c_in_i : std_logic;

-- signal c_out_buf : std_logic;

signal b_buf_tmp : std_logic_vector(1023 downto 0);

signal k,j : integer;

signal a_buf, a_exp, b_buf, m_buf, n_buf_not_1, n_buf_not_2 : std_logic_vector(1023 downto 0);

signal reset_l_1 : std_logic;

type add_state is (idle, cal_k, add1, mod1, shift, mod2, inc_j, output);

signal state, nxstate : add_state;

begin

my_add_sub_1 : add_sub_1024

   port map (

             clk => clk,

             reset_l => reset_l_1,

             start => add_start_1,

             ready => add_ready_1,

             A => a_i,

             B => b_i_1,

             C_IN => c_in_i,

             C_OUT => c_out_i_1,

             ADD => add_i,

             s_valid => s_valid_i_1,

             S => s_i_1);

my_add_sub_2 : add_sub_1024

   port map (

             clk => clk,

             reset_l => reset_l_1,

             start => add_start_2,

             ready => add_ready_2,

             A => a_i,

             B => b_i_2,

             C_IN => c_in_i,

             C_OUT => c_out_i_2,

             ADD => add_i,

             s_valid => s_valid_i_2,

             S => s_i_2);

process(clk)

begin

  if clk'event and clk = '1' then

    reset_l_1 <= reset_l;

  end if;

end process;

process(clk)

begin

  if clk'event and clk = '1' then

    if reset_l_1 = '0' then

      state <= idle;

    else

      state <= nxstate;

    end if;

  end if;

end process;

mod_mult_fsm: process(k, j, state, reset_l_1, start, s_valid_i_1, a_exp, b_buf, b_buf_tmp)

begin

  nxstate <= state;

  case state is

    when idle => if reset_l_1 = '1' and start = '1' then

                   nxstate <= cal_k;

                 end if;

    when cal_k => if k /= 0 then

                    if b_buf_tmp(1023) = '1' then

                      if b_buf(0) = '1' then

                        nxstate <= add1;

                      else

                        nxstate <= shift;

                      end if;

                    end if;

                  else

                    nxstate <= output;

                  end if;

    when add1 => if s_valid_i_1 = '1'then

                   if c_out_i_1 = '1' then

                     nxstate <= mod1;

                   else

                     nxstate <= shift;

                   end if;