Проектирование специализированного микроконтроллера, реализующего полнофункциональную RSA схему шифрования, страница 10

                       c_in_i <= c_out_i;

        when level25 => s(831 downto 800) <= s_i;

                       a_i <= a_buf(831 downto 800);

                       b_i <= b_buf(831 downto 800);

                       c_in_i <= c_out_i;

        when level26 => s(863 downto 832) <= s_i;

                       a_i <= a_buf(863 downto 832);

                       b_i <= b_buf(863 downto 832);

                       c_in_i <= c_out_i;

        when level27 => s(895 downto 864) <= s_i;

                       a_i <= a_buf(895 downto 864);

                       b_i <= b_buf(895 downto 864);

                       c_in_i <= c_out_i;

        when level28 => s(927 downto 896) <= s_i;

                       a_i <= a_buf(927 downto 896);

                       b_i <= b_buf(927 downto 896);

                       c_in_i <= c_out_i;

        when level29 => s(959 downto 928) <= s_i;

                       a_i <= a_buf(959 downto 928);

                       b_i <= b_buf(959 downto 928);

                       c_in_i <= c_out_i;

        when level30 => s(991 downto 960) <= s_i;

                       a_i <= a_buf(991 downto 960);

                       b_i <= b_buf(991 downto 960);

                       c_in_i <= c_out_i;

        when level31 => s(1023 downto 992) <= s_i;

                        c_out <= c_out_i;

                        s_valid <= '1';

        when others => null;

      end case;

    end if;

  end if;

end process;

end architecture;

Текст файла «div_1024.vhd» :

-- 1024-bit Division

-- d = a/b, r = a%b, a, d are 1024-bit numbers, r, b are small numbers

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity div_1024 is

  port (

        clk : in std_logic;

        reset_l : in std_logic;

        start : in std_logic;

        ready : out std_logic;

        A: IN std_logic_VECTOR(1023 downto 0);

        B: IN std_logic_VECTOR(11 downto 0);

        d_valid : out std_logic;

        d: OUT std_logic_VECTOR(1023 downto 0);

        r: OUT std_logic_VECTOR(11 downto 0)); -- remainder

end div_1024;

architecture my_div of div_1024 is

signal k,j : integer;

signal a_buf, d_buf : std_logic_vector(1023 downto 0);

signal a_part, b_buf: std_logic_vector(11 downto 0);

signal reset_l_1 : std_logic;

type div_state is (idle, cal_k, shift, sub, output);

signal state, nxstate : div_state;

begin

process(clk)

begin

  if clk'event and clk = '1' then

    reset_l_1 <= reset_l;

  end if;

end process;

process(clk)

begin

  if clk'event and clk = '1' then

    if reset_l_1 = '0' then

      state <= idle;

    else

      state <= nxstate;

    end if;

  end if;

end process;

div_fsm: process(k, j, state, reset_l_1, start, b_buf)

begin

  nxstate <= state;

  case state is

    when idle => if reset_l_1 = '1' and start = '1' then

                   nxstate <= cal_k;

                 end if;

    when cal_k => if a_buf(1023) = '1' then

                    nxstate <= shift;

                  end if;

    when shift => if k >= j then

                    if j = 1 then

                      nxstate <= sub;

                    end if;

                  else

                    nxstate <= output;

                  end if;

    when sub => nxstate <= shift;

    when output => nxstate <= idle;

 

    when others => nxstate <= idle;

  end case;

end process div_fsm;

process(clk)

begin

  if clk'event and clk = '1' then

    if reset_l_1 = '0' then

      d <= (others => '0');

      r <= (others => '0');

      ready <= '0';

      d_valid <= '0';

      k <= 0;

      j <= 0;

      a_part <= (others => '0');

      a_buf <= (others => '0');

      b_buf <= (others => '0');

      d_buf <= (others => '0');

    else

      ready <= '0';

      d_valid <= '0';

      case state is

        when idle => k <= 1024;

                     j <= 0;

                     ready <= '1';