Проектирование цифровых устройств при помощи языка VHDL. Описание работы компонентов схемы. Моделирование элементов схемы, страница 9

d:in STD_LOGIC_VECTOR(3 DOWNTO 0);

q:out STD_LOGIC_VECTOR(3 DOWNTO 0)

);

end component;

component k561ir9 is

port(

D: in STD_LOGIC_VECTOR(3 downto 0);

J: in STD_LOGIC;

K_inv: in STD_LOGIC;

C: in STD_LOGIC;

R: in STD_LOGIC;

A: in STD_LOGIC;

B: in STD_LOGIC;

Q: out STD_LOGIC_VECTOR(3 downto 0)

);

end component;

component k555ie5 is

port(

c1:in std_logic;

c2:in std_logic;

r1:in std_logic;

r2:in std_logic;

q:out std_logic_vector(3 downto 0)

);

end component;

component k561tm3 is

port(

d:in std_logic;

c:in std_logic;

r:in std_logic;

s:in std_logic;

q:out std_logic;

q_inv:out std_logic

);

end component;

Signal sg1,sg2,sg3,sg4,sg5,sg6,sg7,

sg8,sg9,sg10,sg11,sg12,sg13,

sg14,sg15,sg16,sg17,sg18,sg19,

sg20,sg21,sg22,sg23,sg24,sg25,

sg26,sg27,sg28,sg29, sg30,sg31,

sg32,sg33,sg34,sg35,sg36,sg37,

sg38,sg39,sg40,sg41,sg42,sg43,

sg44,sg45, sg46,sg47,sg48,sg49,

sg50,sg51,sg52,sg53,sg54,sg55,

sg56,sg57,sg58,sg59,sg60,sg61,

sg62,sg63,sg64,sg65,sg66,sg67,

sg68,sg69,sg70,sg71,sg72,sg73,

sg74,sg75,sg76,sg77,sg78,sg79,

sg80,sg81,sg82,sg83,sg84,sg85,sg86,sg87,sg88,sg89,sg90:STD_LOGIC;

begin

dd1_1:k561ln1

port map(zq1,'0','0',sg1);

dd1_4:k561ln1

port map(sg2,'0','0',sg89);

dd1_2:k561ln1

port map(sg3,'0','0',sg4);

dd1_3:k561ln1

port map(k4,'0','0',sg5);

dd2_1:k555la3

port map(k13,k13,sg6);

dd2_2:k555la3

port map(sg6,sg4,sg7);

dd2_3:k555la3

port map(sg8,sg8,sg9);

dd3_1:k561tm3

port map(sg10,sg1,'0','0',sg2,sg10);

dd3_2:k561tm3

port map(sg13,sg12,'0','0',sg14,sg13);

dd15_1:k561tm3

port map(sg15,sg14,'0','0',sg16,sg15);

dd15_2:k561tm3

port map(d=>sg11,c=>sg17,r=>sg11,s=>sg11,q_inv=>sg11);

dd4_1:k561lp2

port map(k18,'0',sg18);

dd4_2:k561lp2

port map(k8,k4,sg19);

dd4_3:k561lp2

port map(sg11,sg12,sg20);

dd5:k555ie6

port map(r=>k2,v=>sg9,c1=>sg21,c2=>'1',d(0)=>sg5,

d(1)=>k4,d(2)=>k18,d(3)=>k2,p=>sg22,

q(0)=>sg23,q(1)=>sg24,q(2)=>sg25,q(3)=>sg26);

dd6:k561ie11

port map(r=>sg27,po_inv=>'0',pm=>k18,v=>sg8,

c=>sg22,d(0)=>sg5,d(1)=>k4,d(2)=>k18,d(3)=>'0',

q(0)=>sg29,q(1)=>sg27,q(2)=>sg30,q(3)=>sg31);

dd7:k561ie11

port map(r=>sg28,po_inv=>'0',pm=>k18,v=>sg8,

c=>sg27,d(0)=>sg5,d(1)=>k4,d(2)=>k18,d(3)=>'0',

q(0)=>sg32,q(1)=>sg28,q(2)=>sg33,q(3)=>sg34);

dd8:k561ie11

port map(r=>sg35,po_inv=>'0',pm=>k18,v=>sg8,

c=>sg28,d(0)=>sg5,d(1)=>k4,d(2)=>k18,d(3)=>'0',

q(0)=>sg36,q(1)=>sg35,q(2)=>sg37,q(3)=>sg38);

dd21:k561ie11        

port map(r=>sg39,po_inv=>'0',pm=>k18,v=>sg8,

c=>sg40,d(0)=>sg5,d(1)=>k4,d(2)=>k18,d(3)=>'0',

q(0)=>sg41,q(1)=>sg39,q(2)=>sg42,q(3)=>sg43);

dd22:k561ie11

port map(r=>sg40,po_inv=>'0',pm=>k18,v=>sg8,

c=>sg35,d(0)=>sg5,d(1)=>k4,d(2)=>k18,d(3)=>'0',

q(0)=>sg44,q(1)=>sg40,q(2)=>sg45,q(3)=>sg46);

dd9:k555ie5

port map(c1=>sg7,c2=>sg47,r1=>sg8,r2=>sg8,q(0)=>sg47,q(1)=>sg90,q(2)=>sg90,q(3)=>sg21);

dd10_v:k561ie10

port map(r=>sg18,c=>'0',v=>sg2,q(0)=>sg12,q(1)=>sg90,q(2)=>sg90,q(3)=>sg48);

dd10_n:k561ie10

port map(r=>sg18,c=>'0',v=>sg48,q(0)=>sg90,q(1)=>sg90,q(2)=>sg90,q(3)=>sg12);

dd11:k561ir9

port map(D(0)=>sg25,D(1)=>sg24,D(2)=>sg23,D(3)=>sg26,J=>sg49,

K_inv=>sg49,C=>sg20,R=>'0',A=>sg50,B=>k18,q(0)=>sg90,q(1)=>sg90,

q(3)=>sg90,q(2)=>sg51);

dd12:k561ir9

port map(D(0)=>sg30,D(1)=>sg27,D(2)=>sg29,D(3)=>sg31,J=>sg51,

K_inv=>sg51,C=>sg20,R=>'0',A=>sg50,B=>k18,q(0)=>sg90,q(1)=>sg90,

q(3)=>sg90,q(2)=>sg52);

dd13:k561ir9