Проектирование цифровых устройств при помощи языка VHDL. Описание работы компонентов схемы. Моделирование элементов схемы, страница 7

x3:in std_logic;

y:out std_logic

);

end k561lp13;

architecture k561lp13 of k561lp13 is

begin

process(x1,x2,x3)

variable k:std_logic;

begin

k:='0';

if ((x1 and x2)='1')or((x1 and x3)='1')or((x3 and x2)='1')then

k:='1';

end if;

y<=transport k after 160ns;

end process;

end k561lp13;

K561tm3

library IEEE;

use IEEE.std_logic_1164.all;

entity k561tm3 is

port(

d:in std_logic;

c:in std_logic;

r:in std_logic;

s:in std_logic;

q:out std_logic;

q_inv:out std_logic

);

end k561tm3;

architecture k561tm3 of k561tm3 is

begin

process(d,c,r,s)

variable q_dop:std_logic;

begin

if s=r then

if c=r or c'event or r'event then

q_dop:=d;

end if;

end if;

if q_dop='U' then

q_dop:='0';

end if;

q<=transport q_dop after 560ns;

q_inv<=transport not(q_dop) after 560ns;

end process;

end k561tm3; 

K561ie8

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity k561ie8 is

port(

r:in std_logic;

c1:in std_logic;

c2_inv:in std_logic;

q:out std_logic_vector(0 to 9)

);

end k561ie8;

architecture k561ie8 of k561ie8 is

begin

process(r,c1,c2_inv)

variable i:integer;

variable q_dop:std_logic_vector(0 to 9);

begin

if q_dop="UUUUUUUUUU" then

i:=-1;

end if;

q_dop:="0000000000";

if r='1' then

q_dop:="1000000000";

i:=i+1;

else

if (c1='1'and c1'event and c2_inv='0')or(c2_inv='0' and        c2_inv'event and c1='1')then

q_dop:="0000000000";

i:=i+1;

q_dop(abs(i rem 10)):='1';

end if;

end if;

q<=transport q_dop after 350ns;

end process;

end k561ie8;

K561ie9

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity k561ie9 is

port(

r:in std_logic;

c:in std_logic;

v:in std_logic;

q:out std_logic_vector(7 downto 0)

);

end k561ie9;

architecture k561ie9 of k561ie9 is

begin

process(r,c,v)

variable k,i,j:integer;

variable q_dop:std_logic_vector(7 downto 0);

begin

if c='U'or v='U' then

q_dop:="00000000";

k:=0;

end if;

if k>36 then

k:=1;

end if;

if k/=17 and k/=18 and k/=19 then

if (c='1' and c'event and v='0')or(v='1'and v'event and c='1') then

q_dop:="00000000";

q_dop(abs(k rem 8)):='1';

k:=k+1;

end if;

end if;

if k=17 then

if c='1' and v='0'and r='0' then

q_dop:="00000010";

k:=k+1;

end if;

end if;

if k=18 then

if c='0' and v='0' and r='0'then

q_dop:="00000001";

k:=k+1;

end if;

end if;

if k=19 then

if c='1' and v='0' and r='1'then

q_dop:="00000001";

k:=k+1;

end if;

end if;

if k=35 then

if c='1'and v='0'and r='0'then

q_dop:="10000100";

k:=k+1;

end if;

end if;

if k=36 then

if c='1'and v='1'and r='0'then

q_dop:="10000100";

k:=k+1;

end if;

end if;

q<=transport q_dop after 500ns;

end process;

end k561ie9;

K561ie10

library IEEE;

use IEEE.std_logic_1164.all;

entity k561ie10 is

port (

r: in STD_LOGIC;

c: in STD_LOGIC;

v: in STD_LOGIC;

q: out STD_LOGIC_VECTOR (3 downto 0)

);

end k561ie10;

architecture k561ie10 of k561ie10 is

begin

process (r,c,v)

variable cntr,tmp: integer;

variable q_int:STD_LOGIC_VECTOR (3 downto 0);

begin

if (c='1' and c'event and v='1') or (c='0' and v='0' and v'event) then

cntr:=cntr+1;

if cntr=15 then

cntr:=0;

end if;

end if;

if r='1' then

cntr:=0;

end if;

tmp:=cntr;

q_int:="0000";

if tmp>=8 then

tmp:=tmp-8;

q_int(3):='1';

end if;

if tmp>=4 then

tmp:=tmp-4;

q_int(2):='1';

end if;

if tmp>=2 then

tmp:=tmp-2;

q_int(1):='1';

end if;

if tmp>=1 then

q_int(0):='1';

end if;

q<=transport q_int after 500 ns;

end process;     

end k561ie10;

K561ie11

library IEEE;

use IEEE.std_logic_1164.all;

entity k561ie11 is

port(

r:in STD_LOGIC;

po_inv:in STD_LOGIC;

pm:in STD_LOGIC;

v:in STD_LOGIC;

c:in STD_LOGIC;

d:in STD_LOGIC_VECTOR(3 DOWNTO 0);

q:out STD_LOGIC_VECTOR(3 DOWNTO 0)