Проектирование цифровых устройств при помощи языка VHDL. Описание работы компонентов схемы. Моделирование элементов схемы, страница 8

);

end k561ie11;

architecture k561ie11 of k561ie11 is

begin

process (r,po_inv,pm,v,c,d)

variable i,j,k:integer;

variable q_dop: STD_LOGIC_VECTOR (3 downto 0);

begin

if q_dop="UUUU" then

q_dop:="0000";

end if;

if r='1' then

q_dop:="0000";

else

if v='1' then

q_dop:=d;

else

if po_inv='0' and c='1' and c'event and pm='1'then

i:=0;

j:=1;

loop

if q_dop(i)='1' then

q_dop(i):='0';

else

q_dop(i):='1';

j:=0;

end if;

i:=i+1;

exit when (i>3or j<1);

end loop;

end if;

if po_inv='0' and c='1' and c'event and pm='0' then

i:=0;

j:=1;

loop

if q_dop(i)='0' then

q_dop(i):='1';

else

q_dop(i):='0';

j:=0;

end if;

i:=i+1;

exit when (i>3or j<1);

end loop;

end if;

end if;

end if;

q<=transport q_dop after 120ns;

end process;

end k561ie11;

K561ir9

library IEEE;

use IEEE.std_logic_1164.all;

entity k561ir9 is

port(

D: in STD_LOGIC_VECTOR(3 downto 0);

J: in STD_LOGIC;

K_inv: in STD_LOGIC;

C: in STD_LOGIC;

R: in STD_LOGIC;

A: in STD_LOGIC;

B: in STD_LOGIC;

Q: out STD_LOGIC_VECTOR(3 downto 0)

);

end k561ir9;

architecture k561ir9 of k561ir9 is

begin

Process (D,J,K_inv,C,R,A,B)

Variable q_dop,g:STD_LOGIC_VECTOR (3 downto 0);

Variable f:STD_LOGIC;

Variable i:integer;

Begin

If c='1' and c'event then

If A='1' then

q_dop:=D;

else

f:=q_dop(3);

q_dop(3):=q_dop(2);

q_dop(2):=q_dop(1);

q_dop(1):=q_dop(0);

q_dop(0):=f;

end if;

If J='1' and k_inv='0'then

i:=1;

f:=q_dop(3);

loop

g:=q_dop;

q_dop(i):=not g(i-1);

i:=i+1;

exit when i>3;

end loop;

q_dop(0):=f;

End if;

If K_inv='0' then

q_dop(0):='0';

End if;

End if;

If R='1' then

q_dop:="0000";

End if;

If q_dop="UUUU" then

q_dop:="0000";

End if;

If B='1' then

Q<=transport q_dop after 410ns;

else

Q<=transport not q_dop after 410ns;

End if;

end process;

end k561ir9;

2.2 Моделирование схемы.

library IEEE;

use IEEE.std_logic_1164.all;

entity shema is

port(zq1:in std_logic;

k2:in std_logic;

k4:in std_logic;

k8:in std_logic;

k13:in std_logic;

k18:in std_logic;

p1:out std_logic;

p2:out std_logic;

p3:out std_logic;

p6:out std_logic;

k7:out std_logic;

p8:out std_logic;

p4:out std_logic;

p5:out std_logic;

H:out std_logic;

zap:out std_logic;

a:out std_logic;

b:out std_logic;

c:out std_logic;

d:out std_logic;

e:out std_logic;

f:out std_logic;

g:out std_logic

);

end shema;

architecture shema of shema is

component k555la3 is

port(

x1:in STD_LOGIC;

x2:in STD_LOGIC;

y:out STD_LOGIC

);

end component;

component k514id2 is

port(

d:in STD_LOGIC_VECTOR(3 downto 0);

q:out std_logic_vector(6 downto 0)

);

end component;

component k555ie6 is

port(

r:in std_logic;

v:in std_logic;

c1:in std_logic;

c2:in std_logic;

d:in STD_LOGIC_VECTOR(3 downto 0);

b:out std_logic;

p:out std_logic;

q:out std_logic_vector(3 downto 0)

);

end component;

component k561ln1 is

port(

d:in STD_LOGIC;

c:in STD_LOGIC;

e:in STD_LOGIC;

q:out std_logic

);

end component;

component k561lp2 is

port(

x1:in std_logic;

x2:in std_logic;

y:out std_logic

);

end component;     

component k561ie8 is

port(

r:in std_logic;

c1:in std_logic;

c2_inv:in std_logic;

q:out std_logic_vector(0 to 9)

);

end component;

component k561lp13 is

port(

x1:in std_logic;

x2:in std_logic;

x3:in std_logic;

y:out std_logic

);

end component;

component k561ie9 is

port(

r:in std_logic;

c:in std_logic;

v:in std_logic;

q:out std_logic_vector(0 to 7)

);

end component;

component k561ie10 is

port(

r: in STD_LOGIC;

c: in STD_LOGIC;

v: in STD_LOGIC;

q: out STD_LOGIC_VECTOR (3 downto 0)

);

end component;

component k561ie11 is

port(

r:in STD_LOGIC;

po_inv:in STD_LOGIC;

pm:in STD_LOGIC;

v:in STD_LOGIC;

c:in STD_LOGIC;