when "0101"=>q<=transport"0001101"after 24ns;
when "1101"=>q<=transport"0011001"after 24ns;
when "0011"=>q<=transport"0100011"after 24ns;
when "1011"=>q<=transport"1001011"after 24ns;
when "0111"=>q<=transport"0001111"after 24ns;
when others=>q<=transport"0000000"after 24ns;
end case;
end process;
end k514id2;
K555la3.
library IEEE;
use IEEE.std_logic_1164.all;
entity K555LA3 is
port(
x1:in STD_LOGIC;
x2:in STD_LOGIC;
y:out STD_LOGIC
);
end K555LA3;
architecture K555LA3 of K555LA3 is
begin
process(x1,x2)
begin
y<=transport x1 nand x2 after 20 ns;
end process;
end K555LA3;
K555ie5.
library IEEE
use IEEE.std_logic_1164.all
entity k555ie5 is
port(
c1:in std_logic;
c2:in std_logic:
r1:in std_logic;
r2:in std_logic;
q:out std_logic_vector(3 downto 0)
);
end k555ie5;
architecture k555ie5 of k555ie5 is
begin
process(c1,c2,r1,r2)
variable k,j:integer;
variable q_dop:std_logic_vector(3 downto 0);
begin
if r1='1' and r2='1' then
q_dop:="0000";
else
if (c1='1' and c1'event)or(c2='1' and c2'event) then
j:=j+1;
q_dop:="0000";
k:=(j rem 16);
if k>=8 then
k:=k-8;
q_dop(3):='1';
end if;
if k>=4 then
k:=k-4;
q_dop(2):='1';
end if;
if k>=2 then
k:=k-2;
q_dop(1):='1';
end if;
if k=1 then
q_dop(0):='1';
end if;
end if;
end if;
q<=q_dop;
end process;
end k555ie5;
K555ie6.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity k555ie6 is
port(
r:in std_logic;
v:in std_logic;
c1:in std_logic;
c2:in std_logic;
d:in STD_LOGIC_VECTOR(3 downto 0);
b:out std_logic;
p:out std_logic;
q:out std_logic_vector(3 downto 0)
);
end k555ie6;
architecture k555ie6 of k555ie6 is
begin
process(r,v,c1,c2,d)
variable k,i,j:integer;
variable w:std_logic_vector(3 downto 0);
begin
if w="UUUU" then
w:="0000";
end if;
if r='1' then
w:="0000";
p<='1';
b<=transport c2 after 24ns;
else
if v='0' and d="0000" then
w:="0000";
p<='1';
b<=transport c1 after 24ns;
end if;
if v='0' and d(0)='1' and d(3)='1' then
w:=d;
b<='1';
p<=transport c1 after 24ns;
end if;
if v='1' and c1='1' and c1'event and c2='1' then
i:=0;
j:=1;
loop
if w(i)='1' then
w(i):='0';
else
w(i):='1';
j:=0;
end if;
i:=i+1;
exit when ((j<1)or(i>3));
end loop;
b<=transport '1' after 24 ns;
p<=transport '1' after 24 ns;
end if;
if v='1' and c2='1' and c2'event and c1='1' then
j:=1;
i:=0;
loop
if w(i)='0' then
w(i):='1';
else
w(i):='0';
j:=0;
end if;
i:=i+1;
exit when ((j<1)or(i>3));
end loop;
b<=transport '1' after 24 ns;
p<=transport '1' after 24 ns;
end if;
end if;
q<=transport w after 38ns;
end process;
end k555ie6;
K561ln1.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity k561ln1 is
port(
d:in STD_LOGIC;
c:in STD_LOGIC;
e:in STD_LOGIC;
q:out std_logic
);
end k561ln1;
architecture k561ln1 of k561ln1 is
begin
process(d,c,e)
begin
if e='1' then
q<=transport 'Z' after 450 ns;
else
if c='1' then
q<=transport '0' after 450 ns;
else q<=transport not d after 450 ns;
end if;
end if;
end process;
end k561ln1;
K561lp2.
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity k561lp2 is
port(
x1:in std_logic;
x2:in std_logic;
y:out std_logic
);
end k561lp2;
architecture k561lp2 of k561lp2 is
begin
process(x1,x2)
begin
if x1=x2 then
y<=transport '0' after 225ns;
else
y<=transport '1' after 225ns;
end if;
end process;
end k561lp2;
К561lp13
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity k561lp13 is
port(
x1:in std_logic;
x2:in std_logic;
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