Языки описания аппаратуры, методические указания по лабораторным работам, страница 10

end or2;

-- ОПИСАНИЕ КОМБИНАЦИОННОГО ЭЛЕМЕНТА

library IEEE;

use IEEE.std_logic_1164.all;

entity component_1 is

       port (

             x1: in STD_LOGIC;

             x2: in STD_LOGIC;

             x3: in STD_LOGIC;

             x4: in STD_LOGIC;

             y1: out STD_LOGIC;

             y2: out STD_LOGIC;

             y3: out STD_LOGIC

       );

end component_1;

architecture strict of component_1 is

   component invertor is

          port (in std_logic;

          o:out std_logic);

   end component;

   component and2 is

          port (

             i1: in STD_LOGIC;

             i2: in STD_LOGIC;

             o: out STD_LOGIC

       );

   end component;

   component and3 is

              port (

             i1: in STD_LOGIC;

             i2: in STD_LOGIC;

             i3: in STD_LOGIC;

             o: out STD_LOGIC

       )

    end component;

    component or2 is

              port (

             i1: in STD_LOGIC;

             i2: in STD_LOGIC;

             o: out STD_LOGIC

       );

   end component;

   component or3 is

              port (

             i1: in STD_LOGIC;

             i2: in STD_LOGIC;

             i3: in STD_LOGIC;

             o: out STD_LOGIC

       );

   end component;

   signal  nx1, nx2, nx3, nx4, T1, T2, T3, T4, T5, T6, T7, T8: std_logic;

   begin

          I1: invertor port map (x1,nx1);

          I2: invertor port map (x2,nx2);

          I3: invertor port map (x3,nx3);

          I4: invertor port map (x4,nx4);     

          A1: and2 port map (x3,nx4,T1);

          A2: and3 port map (nx1,x2,nx3,T2);

          o1: or2 port map (T1,T2,y1);

          A3: and2 port map (nx2,nx3,T3);

          A4: and3 port map (x1,x2,x4,T4);

          A5: and2 port map (nx1,T6,T5);

          o2: or3 port map (T3,T4,T5,y2);

          A6: and2 port map (nx2,x4,T6);