Создание структурных и поведенческих моделей исследуемого цифрового узла (элемент К555IM6 (двоичный 4-разрядный сумматор)) в пакетах DesignLab 8, OrCad 9.1, страница 8

.model D_LS86_2 ugate (

+          tplhty=0ns      tplhmx=0ns

+          tphlty=0ns      tphlmx=0ns

+          )

.model D_LS86_3 ugate (

+          tphlty=0ns      tphlmx=24ns

+          tplhmx=24ns

+          )

*$

*---------

* K555LE1  Quadruple 2-input Positive-Nor Gates

*

* The TTL Data Book, Vol 2, 1985, TI

* tdn    06/23/89         Update interface and model names

*

.subckt K555LE1  IN1 IN2 OUT1

+          optional: DPWR=$G_DPWR DGND=$G_DGND

+          params: MNTYMXDLY=0 IO_LEVEL=0

U1 nor(2) DPWR DGND

+          IN1 IN2 OUT1

+          D_LS02 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.ends

*

.model D_LS02 ugate (

+          tplhty=0ns      tplhmx=0ns

+          tphlty=0ns      tphlmx=0ns

+          )

*$

*---------

* K555LI3  Triple 3-input Positive-And Gates

*

* The TTL Data Book, Vol 2, 1985, TI

* tdn    06/23/89         Update interface and model names

*

.subckt K555LI3  IN1 IN2 IN3 OUT1

+          optional: DPWR=$G_DPWR DGND=$G_DGND

+          params: MNTYMXDLY=0 IO_LEVEL=0

U1 and(3) DPWR DGND

+          IN1 IN2 IN3 OUT1

+          D_LS11 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.ends

*

.model D_LS11 ugate (

+          tplhty=0ns      tplhmx=0ns

+          tphlty=0ns      tphlmx=0ns

+          )

*$

*---------

* K555LI6  Dual 4-input Positive-And Gates

*

* The TTL Data Book, Vol 2, 1985, TI

* tdn    06/26/89         Update interface and model names

*

.subckt K555LI6  IN1 IN2 IN3 IN4 OUT1

+          optional: DPWR=$G_DPWR DGND=$G_DGND

+          params: MNTYMXDLY=0 IO_LEVEL=0

U1 and(4) DPWR DGND

+          IN1 IN2 IN3 IN4 OUT1

+          D_LS21 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.ends

*

.model D_LS21 ugate (

+          tplhty=0ns      tplhmx=0ns

+          tphlty=0ns      tphlmx=0ns

+          )

*$

*---------

* K555LE7  DUAL 5-INPUT POSITIVE-NOR GATES.

*

* The TTL Data Book, Vol 2, 1985, TI

* tvh    07/5/89           Update interface and model names

*

.subckt K555LE7  IN1 IN2 IN3 IN4 IN5 OUT1

+          optional: DPWR=$G_DPWR DGND=$G_DGND

+          params: MNTYMXDLY=0 IO_LEVEL=0

U1 nor(5) DPWR DGND

+          IN1 IN2 IN3 IN4 IN5 OUT1

+          D_S260 IO_S MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.ends

*

.model D_S260 ugate (

+          TPLHTY=0NS           TPLHMX=17NS

+          TPHLTY=0NS           TPHLMX=17NS

+          tphlmn=0ns    tplhmn=0ns

+          )

*

*$

*---------

* K555LA12  Quadruple 2-input Positive-Nand Buffers

*

* The TTL Data Book, Vol 2, 1985, TI

* tdn    06/26/89         Update interface and model names

*

.subckt K555LA12  IN1 IN2 OUT1

+          optional: DPWR=$G_DPWR DGND=$G_DGND

+          params: MNTYMXDLY=0 IO_LEVEL=0

U1 nand(2) DPWR DGND

+          IN1 IN2 OUT1

+          D_LS37 IO_LS MNTYMXDLY={MNTYMXDLY} IO_LEVEL={IO_LEVEL}

.ends

*

.model D_LS37 ugate (

+          tplhty=0ns      tplhmx=0ns

+          tphlty=0ns      tphlmx=0ns

+          )

*$

Приложение 2. VHDL-модели элементов схемы

LIBRARY ieee;

USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \K555LE1\ IS PORT(

            \IN1_-1\ : IN std_logic;

            \IN2_-1\ : IN std_logic;

            \OUT1_-1\ : OUT std_logic;

            VCC : IN std_logic;

            GND : IN std_logic;

            \IN1_-2\ : IN std_logic;

            \IN2_-2\ : IN std_logic;

            \OUT1_-2\ : OUT std_logic;

            \IN1_-3\ : IN std_logic;

            \IN2_-3\ : IN std_logic;

            \OUT1_-3\ : OUT std_logic;

            \IN1_-4\ : IN std_logic;

            \IN2_-4\ : IN std_logic;

            \OUT1_-4\ : OUT std_logic

); END \K555LE1\;

ARCHITECTURE model OF \K555LE1\ IS

    BEGIN

    \OUT1_-1\ <= NOT ( \IN1_-1\ OR \IN2_-1\ );