Проектирование цифрового узла 155КП1, страница 8

+          PINDLY:

+          Y = {

+          CASE(

+          FIRST2&TRN_LH,DELAY(-1,0NS,4NS),

+          FIRST2&TRN_HL,DELAY(-1,0NS,5NS),

+          OVERS&TRN_LH,DELAY(-1,0NS,15NS),

+          OVERS&TRN_HL,DELAY(-1,0NS,8NS),

+          DELAY(-1,6NS,11NS)

+          )

+          }

*

.ends

*

Приложение 2

----------------------------------------------------------------       delay

LIBRARY ieee;                        --элемент задержки на 10 нс

USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY Delay10 IS PORT(

A : IN  std_logic;

Y : OUT  std_logic);

END Delay10;    

ARCHITECTURE model OF Delay10 IS

BEGIN

    Y <= A after 10 ns;

END model;

-------------------------------------------------------------------       LN1

LIBRARY ieee;                        --инвертор

USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \155LN1\ IS PORT(

A : IN  std_logic;

Y : OUT  std_logic);

END \155LN1\;    

ARCHITECTURE model OF \155LN1\ IS

BEGIN

    Y <= not A after 10 ns;

END model;                                                                    

----------------------------------------------------------------        LE1               

LIBRARY ieee;USE                      --элемент ИЛИ

std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \155LE1\ IS PORT(

A : IN  std_logic;

B : IN  std_logic;

Y : OUT  std_logic);

END \155LE1\;

ARCHITECTURE model OF \155LE1\ IS

BEGIN

   Y <= '1' after 5 ns when A='0' and B='0'

                       else '0' after 11 ns;

END model;

 ---------------------------------------------------------------    LA2           

 LIBRARY ieee;                        --элемент 8-И-НЕ

USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \155LA2\ IS PORT(

A : IN  std_logic;

B : IN  std_logic;

C : IN  std_logic;

D : IN  std_logic;

E : IN  std_logic;

F : IN  std_logic;

G : IN  std_logic;

H : IN  std_logic;

Y : OUT  std_logic);

END \155LA2\;

ARCHITECTURE model OF \155LA2\ IS

BEGIN

   Y <= '0' after 5 ns when A='1' and B='1' and C='1' and D='1' and E='1' and F='1' and G='1' and H='1'

                       else '1' after 4 ns;

END model;                                          

 ---------------------------------------------------------------    LA2a           

 LIBRARY ieee;                                                                               --элемент 8-И-НЕ с разными задержками от входов

USE ieee.std_logic_1164.all;

USE work.orcad_prims.all;

ENTITY \155LA2a\ IS PORT(

A : IN  std_logic;

B : IN  std_logic;

C : IN  std_logic;

D : IN  std_logic;

E : IN  std_logic;

F : IN  std_logic;

G : IN  std_logic;

H : IN  std_logic;

Y : OUT  std_logic);

END \155LA2a\;

ARCHITECTURE model OF \155LA2a\ IS

BEGIN

PROCESS (A,B,C,D,E,F,G,H)

BEGIN

                        if (A'event or B'event) then     --если переключились первые два входа, то идет соответствующая задержка

                                    if (A='1' and B='1' and C='1' and D='1' and E='1' and F='1' and G='1' and H='1') then Y <= '0' after 5ns;

                                                else Y <= '1' after 4 ns;      

                                        end if; 

                                    else                               --если переключились другие, то входы задержка другая

                                    if (A='1' and B='1' and C='1' and D='1' and E='1' and F='1' and G='1' and H='1') then Y <= '0' after 8ns;

                                                else Y <= '1' after 15 ns;     

                                        end if; 

                        end if;                                    

end process;  

END model;