If the amount of read data is less than the maxpacketsize (a short packet), the USB core will determine whether to send the data based upon a NAK count limit. This is 4-bit field in the Endpoint Stall Policy register that the user can program with a value indicating how many sequential NAKs should be sent prior to transmitting a short packet. The individual endpoint NAK count (NC bits of the Endpoint NAK Counter Register) is incremented each time a sequential NAK is sent on that particular endpoint. Once this value exceeds the base NAK count value, a short packet is transmitted. The endpoint-specific NC bits are cleared to zero each time a data stage is successfully transmitted for the particular endpoint. This NAK counter system will allow flexibility in how IRPs get retired via short packets.
Along with programming the NK field of the Endpoint Stall Policy Register, the user must program the NE (NAK counter enable) bit to enable this counter function. If this bit is set to zero, the USB core will continuously respond with a NAK handshake to the IN token until the number of bytes in the FIFO is greater than or equal to the maxpacketsize.
Since the DSP is governing the write pointer, it must determine if there is sufficient room in the FIFO for placing new data. Once it has completed writes to the FIFO, it needs to update the Memory Buffer Write Offset register. The DSP can fill the FIFO up to the point where the write pointer is one location behind the read pointer. This will be interpreted as a FIFO full condition by the USB core.
The following example definitions file is for the ADSP-2192 DSP PCI. For the most current definitions file, programs should use the version of this file that comes with the software development tools. The version of the file that appears here is included as a guide only.
/* ----------------------------------------------------------------------------def2192_PCI.h - SYSTEM & IOP REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-2192 Created November 21, 2000. Copyright Analog Devices, Inc.
Note: This file is based on preliminary technical data and is subject to change. Updates will be posted on the Analog Devices FTP site:
ftp.analog.com
-----------------------------------------------------------------------------*/
#ifndef __DEF2192_PCI_H_
#define __DEF2192_PCI_H_
/*Chip Control Registers (DSP IOPAGE=0x00)*/
#define SYSCON 0x00 /* Chip Mode/Status Register */
#define PWRCFG0 0x02 /* Function 0 Power Management */
#define PWRCFG1 0x04 /* Function 1Power Management */
#define PWRCFG2 0x06 /* Function 2 Power Management */
#define PWRP0 0x08 /* DSP 0 Interrupt/Power down */
#define PWRP1 0x0A /* DSP 1 Interrupt/Power down */
#define PLLCTL 0x0C /* DSP PLL Control */
#define REVID 0x0E /* AD‘2 Revision ID (read only) */
/*GPIO Control Registers (DSP IOPAGE=0x00)*/
#define GPIOCFG 0x10 /* GPIO Config Direction Control */
/* 1 = in, 0 = out */
#define GPIOPOL 0x12 /* GPIO Polarity (Inputs: 0 = active hi, */
/* 1 = active lo; Outputs: 0 = CMOS, 1 = Open Drain) */
#define GPIOSTKY 0x14 /* GPIO Sticky: 1 = sticky, 0 = not sticky */
#define GPIOWAKECTL 0x16 /* GPIO Wake Control: 1 = wake-up enabled */
/* requires sticky set */
#define GPIOSTAT 0x18 /* GPIO Status (Read = Pin state; */
/* Write: 0 = clear sticky status, 1 = no effect) */
#define GPIOCTL 0x1A /* GPIO Control(w), Init(r) (Read = Power-on state; */
/* Write : Set state of output pins) */
#define GPIOPUP 0x1C /* GPIO Pull-up Pull-up enable (if input): */
/* 1 = enable, 0 = hi-Z */
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