Host (pci/usb) port. Over view. Host Port Selection. Configuration Spaces. PCI Configuration Space, страница 33

5.  Since the memory FIFOs are circular in behavior, the DSP code that calculates either the amount of free space or the amount of available data may need to take into account the Memory Buffer Size value.

Example

DSP coding steps required to determine the amount of available data in a memory buffer that has been set up for USB OUT transactions (DSP governing the read pointer).

Result = Write pointer – Read pointer

a.  If positive, the result directly indicates the amount of available data to process.

b.  If negative, add the buffer size to the result to determine the amount of available data to process. The negative result indicates that the write pointer must have looped back to the top of the FIFO.

In summary, before the USB host can send traffic to the data Endpoints, they need to be programmed in 2 ways:

•  MCU: Programs the traits of the Endpoints such as type, direction, maxpacketsize, etc.This is accomplished via writes to the Endpoint Description, NAK Counter, and Stall Policy registers. A convenient method of doing this is to have the MCU firmware program these registers prior to responding to USB control traffic for enumeration on the USB bus.

•  DSP: Programs the traits of the DSP DM memory buffers. This is accomplished via IO writes to the Base/Size/Read Offset/Write Offset registers as part of some DSP initialization code.

O UT Tra nsa c tions (Host to De vic e )

For OUT transactions, the write pointer is controlled by the USB core, and the read pointer is governed by the DSP. The read and write pointers both start with a value of zero.

When an OUT transaction arrives for a particular Endpoint, the USB core calculates the difference between the write and read pointers to determine how much room there is in the FIFO. If all the OUT data arrives and the write pointer never catches up to the read pointer, that data will be acknowledged (ACK) and the USB core will update the Memory Buffer Write Offset register. If at any time during the transaction the two pointers collide, the USB block will respond with a NAK indicating that the host must resend the same data packet. The write pointer will remain unchanged.

If for some reason the host sends more data than the maxpacketsize, the USB core will accept it as long as there is sufficient room in the FIFO. The USB core will write data to the FIFO to all free locations until the pointers collide. For example, if the FIFO has 32 free bytes and 64 bytes are sent from the host, the USB core will write the first 32 bytes to the FIFO and block the second 32 bytes. During the handshake, the USB core will send a NAK handshake and rewind the write pointer back to its setting prior to the start of the transaction. The USB core never allows the write pointer to be equal to the read pointer as this indicates FIFO empty. A full FIFO is indicated by the write pointer being one location behind the read pointer.

Since the DSP is governing the read pointer, it must perform a similar calculation to determine if there is sufficient data in the FIFO to begin processing. Once it has consumed some amount of data, the DSP will need to update the Memory Buffer Read Offset register. The DSP code cannot program the read pointer to move beyond the write pointer. The DSP can drain all the data from the FIFO, in which case it can program the read pointer to equal the write pointer. Such a condition indicates to the USB core that this FIFO is empty.

 IN Tra nsa c tions (De vic e to Host)

For IN transactions, the write pointer is controlled by the DSP, and the read pointer is governed by the USB core. The read and write pointers both start with a value of zero.

When an IN transaction arrives for a particular Endpoint, the USB core will again compute how much read data there is available in the FIFO. It will also determine if the amount of read data is greater than or equal to the maxpacketsize. If both conditions are met, the USB core will transfer the data. Upon receiving ACK from the host, the USB core will update the Memory Buffer Read Offset register. The USB core can drain all the data from the FIFO, leaving it empty. It indicates this by setting the read pointer equal to the write pointer.