Другие предметы \ Радиоприемные устройства связи и вещания

Host (pci/usb) port. Over view. Host Port Selection. Configuration Spaces. PCI Configuration Space, страница 2

Address

Name

Reset

Comments

0x17-0x14

Base Address 2

0x08

24-bit DSP Memory Access

0x1B-0x18

Base Address 3

0x08

16-bit DSP Memory Access

0x1F-0x1C

Base Address 4

0x01

I/O access for control registers and DSP memory

0x23-0x20

Base Address 5

0x0

Unimplemented

0x27-0x24

Base Address 6

0x0

Unimplemented

0x2B-0x28

Cardbus CIS Pointer

0x1FF03

CIS RAM Pointer - Function 0 (Read Only).

0x2D-0x2C

Subsystem Vendor ID

0x11D4

Writable from the DSP during initialization

0x2F-0x2E

Subsystem Device ID

0x2192

Writable from the DSP during initialization

0x33-0x30

Expansion ROM Base Address

0x0

Unimplemented

0x34

Capabilities Pointer

0x40

Read-only

0x3C

Interrupt Line

0x0

0x3D

Interrupt Pin

0x1

Uses INTA# Pin

0x3E

Min_Gnt

0x1

Read-only

0x3F

Max_Lat

0x4

Read-only

0x40

Capability ID

0x1

Power Management Capability Identifier

0x41

Next_Cap_Ptr

0x0

Read-only

Table 8-2. PCI Configuration Space (Continued)

Address

Name

Reset

Comments

0x43-0x42

Power Management Capabilities

0x6C22

Writable from the DSP during initialization

0x45-0x44

Power Management Control/ Status

0x0

Bits 15 and 8 initialized only on Power-up

0x46

Power Management Bridge

0x0

Unimplemented

0x47

Power Management Data

0x0

Unimplemented

Inte ra c tions Be twe e n Func tions

Because all functions access and control a single set of resources, potential conflicts may occur in the control specified by the configuration. Table 8-3 on page 8-5 and Table 8-4 on page 8-10 identify the interactions and suggest conflict resolutions. Table 8-3 on page 8-5 identifies the registers in the predefined header space, and Table 8-4 on page 8-10 identifies the interactions in the Power Management registers. Table 8-3. Configuration Space—Function Interactions

Address

Name

Comments

Vendor ID

Separate registers, no interaction

Device ID

Separate registers, no interaction

Command Register

Bit 0

I/O Space Enable

Enables are separate in each function, go along with the function’s base addresses

Command Register

Bit 1

Memory Space Enable

Enables are separate in each function, go along with the function’s base addresses

Table 8-3. Configuration Space—Function Interactions (Continued)

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