Другие предметы \ Радиоприемные устройства связи и вещания

Host (pci/usb) port. Over view. Host Port Selection. Configuration Spaces. PCI Configuration Space, страница 15

Figure 8-5. USB Endpoint Stall Policy Register

The USB Endpoint Stall Policy Register contains the base NAK count and FIFO error policy bits for Endpoints 4-11. The STALL status and Data toggle bits for Endpoints 1-3 are included as well. This register is read/write by the MCU only.      

Table 8-14. USB Endpoint Stall Policy Register

ST[3:1]

A value of 1 means the Endpoint is stalled. ST[1] maps to Endpoint 1, ST[2] maps to Endpoint 2, etc.

TB[3:1]

Toggle bit for Endpoint. Reflects the current state of the DATA toggle bit. ST[1]

maps to Endpoint 1, ST[2] maps to Endpoint 2, etc.

NK[3:0]

Base NAK counter. Determines how many sequential NAKs are issued before sending zero length packet, or a packet less than the maximum packet size, on any given Endpoint.

FE

FIFO error policy. A value of 1 means: Endpoint FIFO is overrun/underrun, STALL Endpoint

LSW

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

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11

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8

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DS

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Figure 8-6. USB Endpoint 1 Code Download Base Address Register

The USB Endpoint 1 Code Download Base Address Register contains an 18 bit address which corresponds to the starting location for DSP code download on Endpoint 1. This register is read/write by the MCU only. The most significant bit (DS bit) selects either DSP1 PM address space (DS=0) or DSP2 PM address space (DS=1).

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DS

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Figure 8-7. USB Endpoint 2 Code Download Base Address Register

The USB Endpoint 2 Code Download Base Address Register contains an 18-bit address that corresponds to the starting location for DSP code download on Endpoint 2. This register is read/write by the MCU only. The most significant bit (DS bit) selects either DSP1 PM address space (DS=0) or DSP2 PM address space (DS=1).

LSW

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