Host (pci/usb) port. Over view. Host Port Selection. Configuration Spaces. PCI Configuration Space, страница 11

•  3 Endpoints dedicated to downloading DSP code

•  8 User-Programmable Endpoints for DSP data

•  4 registers per Data Endpoint to define a DSP memory buffer associated with each Endpoint

•  Support for all four USB transaction types (Bulk, Control, Interrupt, and Isochronous)

•  8051 compatible microcontroller (having 2K bytes of Program Memory ROM, 4K bytes of Program Memory RAM, and 256 bytes of Data Memory RAM) to support flexible descriptor definitions and USB device requests. Application-specific MCU microcode needs to be downloaded through the USB interface.

•  A dedicated hardware block to stream the data into and out of the data Endpoints from the host. This hardware block manages the USB transactions to each data Endpoint and serves as a conduit for the data as it moves from the memory buffers (FIFOs) in DSP memory space. No MCU involvement is required to manage these data pipes.

•  Interaction with the DSP using the DMA and PDC buses.

•  12MB/s (run at full speed)

•  Support for OHCI and UHCI Hosts

Bloc k Dia g ra m of USB Mod ule

Figure 8-2 on page 8-28 shows a block diagram of the USB module in the ADSP-2192. Each element is described in this section.

USB-SIE

This block interfaces to the outside interface. All the USB data traffic goes through it. Its two paths, I/P and O/P, support both control and data traffic flow. On the Receive side, the clock employs recovery, error checking, and bit stuffing as it decodes the NRZ data. On the transmit side, it does the opposite: NRZ encodes it, appends the CRC, bit-stuffs it if necessary, and transmits the data. It also sends out the sync header and end-of-packet fields.

Figure 8-2. ADSP-2192 USB Block Diagram

End p oint 0 C ontrol

This block manages all traffic duties for Endpoint 0, serving as the communication link between the USB host and the MCU. For host-to-device transfers, it notifies the MCU when valid SETUP commands or OUT packet data arrives for processing by the MCU. In responding to device-to-host transfers, it transmits the proper data packet or handshake packet under MCU guidance.

MC U

The MCU is an 8-bit 8051 compatible MCU within the USB. It acts as the controller for the USB block. It handles all the command and data processing for the Endpoint 0. It also parameterizes the DSP code and data Endpoints. There is no involvement in the actual data transfer for the DSP code and data endpoints.

I/O REG Inte rfa c e

This is the 16-bit interface to the internal PDC (Peripheral Device Control) bus. All the writing and reading to and from the I/O space is performed through this interface. PDC is a multiplexed address and Data bus.

DSP DMA Inte rfa c e

This interface is the link between the USB and the internal IDMA bus, which goes into the DSP memory. The serial data collected by the SIE interface is converted into byte-wide packets and sent to DSP DMA interface. Based upon the packet type, program, or Data, the DSP DMA interface converts it into a 3-byte packet (24 bits) or a 2-byte packet (upper 16-bits of the IDMA bus) and then dispatches it to the DSP memory. It also does the retrieval from the Internal Memory 16-bit-wide data, splits it into byte-wide format, and sends it to the SIE. SIE then splits it in serial format and sends it to the host over the serial bus.

DSP C od e /Da ta End p oint C ontrol

This block manages all traffic duties for both DSP code (via Endpoints 1:3) and DSP data (via Endpoints 4:11). All USB data through this block streams directly to and from DSP memory with no involvement from the MCU. The only requirement from the MCU is to program the personalities (transfer type, maximum packet size, direction, etc.) of all the enumerated Endpoints prior to any USB transactions.

Fe a ture s a nd Mod e s

The different functions supported by the USB module are as follows:

End p oint Typ e s