Моделирование электронных схем на языке VHDL. Описание элементов. Логический элемент «НЕ» К155ЛН1, страница 6

);

end TOP;

architecture TOP of TOP is

COMPONENT k155ln1 is

port (

input: in STD_LOGIC;

output_inv: out STD_LOGIC

);

end COMPONENT;

COMPONENT k155tm2 is

port (

r_inv_T1: in STD_LOGIC;

d_T1: in STD_LOGIC;

c_T1: in STD_LOGIC;

s_inv_T1: in STD_LOGIC;

q_T1: out STD_LOGIC;

q_inv_T1: out STD_LOGIC;

r_inv_T2: in STD_LOGIC;

d_T2: in STD_LOGIC;

c_T2: in STD_LOGIC;

s_inv_T2: in STD_LOGIC;

q_T2: out STD_LOGIC;

q_inv_T2: out STD_LOGIC

);

end COMPONENT;

COMPONENT k155ll2 is

port (

input1_LL2: in STD_LOGIC;

input2_LL2: in STD_LOGIC;

output3_LL2: out STD_LOGIC;

input6_LL2: in STD_LOGIC;

input7_LL2: in STD_LOGIC;

output5_LL2: out STD_LOGIC

);

end COMPONENT;

COMPONENT k155la18 is

port (

input1: in STD_LOGIC;

input2: in STD_LOGIC;

input6: in STD_LOGIC;

input7: in STD_LOGIC;

output3_inv: out STD_LOGIC;       

output5_inv: out STD_LOGIC

);

end COMPONENT;

COMPONENT k155ll1 is

port (a1_LL1,b1_LL1,a2_LL1,b2_LL1,a3_LL1,b3_LL1,a4_LL1,b4_LL1: in std_logic;

y1_LL1,y2_LL1,y3_LL1,y4_LL1: out std_logic);

end COMPONENT;

COMPONENT k555la4 is

port (

a1_LA4: in STD_LOGIC;

b1_LA4: in STD_LOGIC;

c1_LA4: in STD_LOGIC;

a2_LA4: in STD_LOGIC;

b2_LA4: in STD_LOGIC;

c2_LA4: in STD_LOGIC;

a3_LA4: in STD_LOGIC;

b3_LA4: in STD_LOGIC;

c3_LA4: in STD_LOGIC;

y1_LA4: out STD_LOGIC;

y2_LA4: out STD_LOGIC;        

y3_LA4: out STD_LOGIC

);

end COMPONENT;

COMPONENT k155la3 is

port (

a1_LA3: in STD_LOGIC;

b1_LA3: in STD_LOGIC;

a2_LA3: in STD_LOGIC;

b2_LA3: in STD_LOGIC;

a3_LA3: in STD_LOGIC;

b3_LA3: in STD_LOGIC;

a4_LA3: in STD_LOGIC;

b4_LA3: in STD_LOGIC;

y1_LA3: out STD_LOGIC;

y2_LA3: out STD_LOGIC;

y3_LA3: out STD_LOGIC;

y4_LA3: out STD_LOGIC

);

end COMPONENT;

COMPONENT k555lp5 is

port (

a1_LP5: in STD_LOGIC;

b1_LP5: in STD_LOGIC;

a2_LP5: in STD_LOGIC;

b2_LP5: in STD_LOGIC;

a3_LP5: in STD_LOGIC;

b3_LP5: in STD_LOGIC;

a4_LP5: in STD_LOGIC;

b4_LP5: in STD_LOGIC;

y1_LP5: out STD_LOGIC;

y2_LP5: out STD_LOGIC;

y3_LP5: out STD_LOGIC;

y4_LP5: out STD_LOGIC

);

end COMPONENT;

COMPONENT K561IE10 is

port (

C0: in STD_LOGIC;

V0: in STD_LOGIC;

R0: in STD_LOGIC;

C1: in STD_LOGIC;

V1: in STD_LOGIC;

R1: in STD_LOGIC;

Q0: out STD_LOGIC_VECTOR (3 downto 0);

Q1: out STD_LOGIC_VECTOR (3 downto 0)

);

end COMPONENT;

COMPONENT k555SP1 is 

port (a3,a2,a1,a0,b3,b2,b1,b0 : in std_ulogic;

aPbout,aBbout,aMbout : out std_ulogic);

end COMPONENT;

signal  ground,one,zero    : std_logic;

signal  PLUS_E,PLUS_5 : std_logic;

signal  PROVOD        : std_logic;

--signal  d5_1_in    : std_logic;

signal  d5_1_d9_1  : std_logic;

signal  d9_1_out   : std_logic;

signal  d9_1_in    : std_logic;

signal  d5_3_d9_1  : std_logic;

signal  d1_d6      : std_logic;

signal  d6_d9_2    : std_logic;

signal  d9_2_d3    : std_logic;

signal  d6_d5_3    : std_logic;

signal  d2_1_d7_1  : std_logic;

signal  d7_1_d5_4  : std_logic;

signal  d5_4_out   : std_logic;

signal  d3_in      : std_logic;

signal  c_t1_plus5 : std_logic;

signal  d3_d8_1    : std_logic;

signal  d3_out     : std_logic;

signal  d3_d8_2    : std_logic;

signal  d3_d2_2    : std_logic;

signal  d8_2_d10   : std_logic;

signal  d2_2_d7_2  : std_logic;

signal  d5_2_d8_1  : std_logic;

signal  d8_1_out   : std_logic;

signal  d4_out1    : std_logic;

signal  d4_out2    : std_logic;

---------------------------------begin

one<='0';

zero<='0';

PLUS_E<='0';

PLUS_5<='1';

D5_1:k155ln1  port  map  (input=>MRDC_INV,

output_inv=>d5_1_d9_1);

D9_1:k555la4  port  map  (  a1_LA4=>d5_1_d9_1,

b1_LA4=>ENRAM,

c1_LA4=>d5_3_d9_1,

a2_LA4=>zero,

b2_LA4=>zero,

c2_LA4=>zero,

a3_LA4=>zero,

b3_LA4=>zero,

c3_LA4=>zero,

y1_LA4=>OE_INV,

y2_LA4=>ground,         

y3_LA4=>ground );

D1:k555SP1  port  map  (a3=>zero,

a2=>zero,

a1=>zero,