---------------------------------4NOTAND
-- File: k155la3.vhd
-- created by Design Wizard: 03/30/04 20:22:45
-library IEEE;
use IEEE.std_logic_1164.all;
entity k155la3 is
port (
a1_LA3: in STD_LOGIC;
b1_LA3: in STD_LOGIC;
a2_LA3: in STD_LOGIC;
b2_LA3: in STD_LOGIC;
a3_LA3: in STD_LOGIC;
b3_LA3: in STD_LOGIC;
a4_LA3: in STD_LOGIC;
b4_LA3: in STD_LOGIC;
y1_LA3: out STD_LOGIC;
y2_LA3: out STD_LOGIC;
y3_LA3: out STD_LOGIC;
y4_LA3: out STD_LOGIC
);
end k155la3;
architecture k155la3 of k155la3 is
begin
y1_LA3 <= transport not(a1_LA3 and b1_LA3) after 27nS;
y2_LA3 <= transport not(a2_LA3 and b2_LA3) after 27nS;
y3_LA3 <= transport not(a3_LA3 and b3_LA3) after 27nS;
y4_LA3 <= transport not(a4_LA3 and b4_LA3) after 27nS;
-- <<enter your statements here>>
end k155la3;
-----------------------------k155ll2
---------------------------------library IEEE;
use IEEE.std_logic_1164.all;
entity k155ll2 is
port (
input1_LL2: in STD_LOGIC;
input2_LL2: in STD_LOGIC;
output3_LL2: out STD_LOGIC;
input6_LL2: in STD_LOGIC;
input7_LL2: in STD_LOGIC;
output5_LL2: out STD_LOGIC
);
end k155ll2;
architecture k155ll2 of k155ll2 is
begin
output3_LL2 <= transport (input1_LL2 or input2_LL2) after 30ns;
output5_LL2 <= transport (input6_LL2 or input7_LL2) after 30ns;
-- <<enter your statements here>>
end k155ll2;
---------------------k555lp5
------------------------4XOR
-- File: k155lp5.vhd
-- created by Design Wizard: 03/30/04 19:48:41
-library IEEE;
use IEEE.std_logic_1164.all;
entity k555lp5 is
port (
a1_LP5: in STD_LOGIC;
b1_LP5: in STD_LOGIC;
a2_LP5: in STD_LOGIC;
b2_LP5: in STD_LOGIC;
a3_LP5: in STD_LOGIC;
b3_LP5: in STD_LOGIC;
a4_LP5: in STD_LOGIC;
b4_LP5: in STD_LOGIC;
y1_LP5: out STD_LOGIC;
y2_LP5: out STD_LOGIC;
y3_LP5: out STD_LOGIC;
y4_LP5: out STD_LOGIC
);
end k555lp5;
architecture k555lp5 of k555lp5 is
begin
y1_LP5 <=transport a1_LP5 xor b1_LP5 after 30nS;
y2_LP5 <=transport a2_LP5 xor b2_LP5 after 30nS;
y3_LP5 <=transport a3_LP5 xor b3_LP5 after 30nS;
y4_LP5 <=transport a4_LP5 xor b4_LP5 after 30nS;
-- <<enter your statements here>>
end k555lp5;
-------------------------k555la4
----------------------------- File: k555la4.vhd
-- created by Design Wizard: 03/30/04 20:08:10
-library IEEE;
use IEEE.std_logic_1164.all;
entity k555la4 is
port (
a1_LA4: in STD_LOGIC;
b1_LA4: in STD_LOGIC;
c1_LA4: in STD_LOGIC;
a2_LA4: in STD_LOGIC;
b2_LA4: in STD_LOGIC;
c2_LA4: in STD_LOGIC;
a3_LA4: in STD_LOGIC;
b3_LA4: in STD_LOGIC;
c3_LA4: in STD_LOGIC;
y1_LA4: out STD_LOGIC;
y2_LA4: out STD_LOGIC;
y3_LA4: out STD_LOGIC
);
end k555la4;
architecture k555la4 of k555la4 is
begin
y1_LA4 <= transport not (a1_LA4 and b1_LA4 and c1_LA4) after 20nS;
y2_LA4 <=transport not (a2_LA4 and b2_LA4 and c2_LA4) after 20nS;
y3_LA4 <=transport not (a3_LA4 and b3_LA4 and c3_LA4) after 20nS;
-- <<enter your statements here>>
end k555la4;
--------------------------TOP.vhd
--------------------------------- File: TOP.vhd
-- created by Design Wizard: 04/11/04 16:38:19
-library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity TOP is
port (
ENRAM: in STD_LOGIC;
MRDC_INV: in STD_LOGIC;
A14: in STD_uLOGIC;
A15: in STD_uLOGIC;
A16: in STD_uLOGIC;
A17: in STD_uLOGIC;
ALE1: in STD_LOGIC;
A18: in STD_LOGIC;
A19: in STD_LOGIC;
CLK: in STD_LOGIC;
AMWC_INV: in STD_LOGIC;
BHE_INV: in STD_LOGIC;
AO: in STD_LOGIC;
OE_INV: out STD_LOGIC;
RAM_EPROM_INV: out STD_LOGIC;
ON_INV_OFF1: out STD_LOGIC;
CMR: out STD_LOGIC;
CAS_INV: out STD_LOGIC;
WE1_INV: out STD_LOGIC;
WE2_INV: out STD_LOGIC;
RAS_INV: out STD_LOGIC;
NONAME1: out STD_LOGIC;
NONAME2: out STD_LOGIC;
RFC: out STD_LOGIC_VECTOR (8 downto 1)
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