Моделирование электронных схем на языке VHDL. Описание элементов. Логический элемент «НЕ» К155ЛН1, страница 3

end if;

q_T1<=transport state_T1 after 30ns;

q_inv_T1<=transport state_inv_T1 after 30ns;

end process;

--------------------process (r_inv_T2,d_T2,c_T2,s_inv_T2)

variable state_T2,state_inv_T2:STD_LOGIC;

begin

if c_T2='1' and c_T2'event then

state_T2:=d_T2;

state_inv_T2:=not state_T2;

end if;

if r_inv_T2='0' and s_inv_T2='1' then

state_T2:='0';

state_inv_T2:='1';

end if;

if r_inv_T2='1' and s_inv_T2='0' then

state_T2:='1';

state_inv_T2:='0';

end if;

if r_inv_T2='0' and s_inv_T2='0' then

state_T2:='1';

state_inv_T2:='1';

end if;

q_T2<=transport state_T2 after 30ns;

q_inv_T2<=transport state_inv_T2 after 30ns;

end process;

-- <<enter your statements here>>

end k155tm2;

-------------------------------K561IE10

---------------------------------  File: K561IE10.vhd

--  created by Design Wizard: 04/11/04 11:06:06

library IEEE;

use IEEE.std_logic_1164.all;

entity K561IE10 is

port (

C0: in STD_LOGIC;

V0: in STD_LOGIC;

R0: in STD_LOGIC;

C1: in STD_LOGIC;

V1: in STD_LOGIC;

R1: in STD_LOGIC;

Q0: out STD_LOGIC_VECTOR (3 downto 0);

Q1: out STD_LOGIC_VECTOR (3 downto 0)

);

end K561IE10;

architecture K561IE10 of K561IE10 is

begin

process(C0,V0,R0) 

variable Q_int: STD_LOGIC_VECTOR (3 downto 0);

variable Qint,tmp:natural;

begin       

if R0='1' then Q_int:="0000" ;

else

if  C0='1' and C0'last_value='0' and V0='1' and R0='0'

then

if Qint<16 then

Qint:= Qint+1;

else

Qint:=0;

end if;

else

if  C0='0' and V0='0' and V0'last_value='1'  and R0='0'

then

if Qint<16 then

Qint:=Qint+1;

else

Qint:=0;

end if;

else

if  C0='0' and C0'last_value='1'  and R0='0'     

then

if Qint<16 then

Qint:= Qint ;

else

Qint:=0;

end if;

else

if    V0='1'and V0'last_value='0'

then

if Qint<16 then

Qint:= Qint ;

else

Qint:=0;

end if;

else

if  C0='1' and C0'last_value='0' and V0='0' and R0='0'

then

if Qint<16 then

Qint:= Qint ;

else

Qint:=0;

end if;

else

if  C0='1' and V0='0' and V0'last_value='1' and R0='0'

then        

if Qint<16 then

Qint:= Qint;

else

Qint:=0;

end if;

if R0='1' then Q_int:="0000" ;

end if;

end if;

end if;

end if;

end if;

end if;

end if; 

end if;

---------tmp:=Qint;

q_int:="0000";

if tmp>=8 then

tmp:=tmp-8;

q_int(3):='1';

end if;

if tmp>=4 then

tmp:=tmp-4;

q_int(2):='1';

end if;

if tmp>=2 then

tmp:=tmp-2;

q_int(1):='1';

end if;

if tmp=1 then

q_int(0):='1';

end if;

--------Q0<= transport Q_int after 80nS;

end process;

process(C1,V1,R1) 

variable Q1_int: STD_LOGIC_VECTOR (3 downto 0);

variable Q1int,tmp1:natural;

begin       

if R1='1' then Q1_int:="0000" ;

else

if  C1='1' and C1'last_value='0' and V1='1' and R1='0'

then

if Q1int<16 then

Q1int:= Q1int+1;

else

Q1int:=0;

end if;

else

if  C1='0' and V1='0' and V1'last_value='1'  and R1='0'

then

if Q1int<16 then

Q1int:=Q1int+1;

else

Q1int:=0;

end if;

else

if  C1='0' and C1'last_value='1'  and R1='0'     

then

if Q1int<16 then

Q1int:= Q1int ;

else

Q1int:=0;

end if;

else

if    V1='1'and V1'last_value='0'

then

if Q1int<16 then

Q1int:= Q1int ;

else

Q1int:=0;

end if;

else

if  C1='1' and C1'last_value='0' and V1='0' and R1='0'

then

if Q1int<16 then

Q1int:= Q1int ;

else

Q1int:=0;

end if;

else

if  C1='1' and V1='0' and V1'last_value='1' and R1='0'

then        

if Q1int<16 then

Q1int:= Q1int;

else

Q1int:=0;

end if;

if R1='1' then Q1_int:="0000" ;

end if;

end if;

end if;

end if;

end if;

end if;

end if; 

end if;

---------tmp1:=Q1int;

q1_int:="0000";

if tmp1>=8 then

tmp1:=tmp1-8;

q1_int(3):='1';

end if;

if tmp1>=4 then

tmp1:=tmp1-4;

q1_int(2):='1';

end if;

if tmp1>=2 then

tmp1:=tmp1-2;

q1_int(1):='1';

end if;