Моделирование электронных схем на языке VHDL. Описание элементов. Логический элемент «НЕ» К155ЛН1, страница 4

if tmp1=1 then

q1_int(0):='1';

end if;

--------Q1<= transport Q1_int after 80nS;

end process;

-- <<enter your statements here>>      

end K561IE10;

---------------------------------------k155SP1

---------------------------------k155SP1-4komparator

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity k555SP1 is 

port (a3,a2,a1,a0,b3,b2,b1,b0 : in std_ulogic;

aPbout,aBbout,aMbout : out std_ulogic);

end k555SP1;

architecture k555SP1 of k555SP1 is

begin

-- CPABHEHIE

process(a3,a2,a1,a0,b3,b2,b1,b0)

begin--else   

-- a3 > b3

if a3 > b3 then

aPbout <= transport '0' after 30nS;

aBbout <= transport '1' after 30nS;--a>b

aMbout <= transport '0' after 30nS;

-- a3 < b3

elsif a3 < b3 then

aPbout <= transport'0' after 30nS;

aBbout <= transport '0' after 30nS;

aMbout <= transport '1' after 30nS;--a<b

-- a3 = b3

else if a3 = b3 then

-- a2 > b2

if a2 > b2 then

aPbout <= transport '0' after 30nS;

aBbout <= transport '1' after 30nS;--a>b

aMbout <= transport '0' after 30nS;

-- a2 < b2

elsif a2 < b2 then

aPbout <= transport'0' after 30nS;

aBbout <= transport '0' after 30nS;

aMbout <= transport '1' after 30nS;--a<b

-- a2 = b2

else if a2 = b2 then

-- a1 > b1

if a1 > b1 then

aPbout <= transport '0' after 30nS;

aBbout <= transport '1' after 30nS;--a>b

aMbout <= transport '0' after 30nS;

-- a1 < b1

elsif a1 < b1 then

aPbout <= transport'0' after 30nS;

aBbout <= transport '0' after 30nS;

aMbout <= transport '1' after 30nS;--a<b

-- a1 = b1

else if a1 = b1 then

-- a0 > b0

if a0 > b0 then

aPbout <= transport '0' after 30nS;

aBbout <= transport '1' after 30nS;--a>b

aMbout <= transport '0' after 30nS;

-- a0 < b0

elsif a0 < b0 then

aPbout <= transport'0' after 30nS;

aBbout <= transport '0' after 30nS;

aMbout <= transport '1' after 30nS;--a<b

--PABHO

elsif a0 = b0 then

aPbout <= transport '1' after 30nS;

aBbout <= transport '0' after 30nS;

aMbout <= transport '0' after 30nS;

elsE

aPbout <= transport 'U' after 30nS;

aBbout <= transport 'U' after 30nS;

aMbout <= transport 'U' after 30nS;

-- KOHEZ  CPABHEHIE

end if;

end if; 

end if;

end if;

end if;

end if;

end if;

end  process;

end k555SP1;

k155ln1

------------------------------k155ln1.VHD

library IEEE;

use IEEE.std_logic_1164.all;

entity k155ln1 is

port (

input: in STD_LOGIC;

output_inv: out STD_LOGIC

);

end k155ln1;

architecture k155ln1 of k155ln1 is

begin

output_inv<=transport not input after 22ns;

-- <<enter your statements here>>

end k155ln1;

----------------------------k155la18

--------------------------library IEEE;

use IEEE.std_logic_1164.all;

entity k155la18 is

port (

input1: in STD_LOGIC;

input2: in STD_LOGIC;

input6: in STD_LOGIC;

input7: in STD_LOGIC;

output3_inv: out STD_LOGIC;       

output5_inv: out STD_LOGIC

);

end k155la18;

architecture k155la18 of k155la18 is

begin

output3_inv<= transport not (input1 and input2) after 27ns;

output5_inv<= transport not (input6 and input7) after 27ns;

-- <<enter your statements here>>

end k155la18;

k155ll1

----------------------------

--k155ll1-4nor

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity k155ll1 is

port (a1_LL1,b1_LL1,a2_LL1,b2_LL1,a3_LL1,b3_LL1,a4_LL1,b4_LL1: in std_logic;

y1_LL1,y2_LL1,y3_LL1,y4_LL1: out std_logic);

end k155ll1;

architecture k155ll1 of k155ll1 is

begin

y1_LL1 <=transport (a1_LL1 or b1_LL1) after 30nS; 

y2_LL1 <=transport (a2_LL1 or b2_LL1) after 30nS;

y3_LL1 <=transport (a3_LL1 or b3_LL1) after 30nS;

y4_LL1 <=transport (a4_LL1 or b4_LL1) after 30nS;

end k155ll1;

-----------------------------k155la3