Проектирование и моделирование VHDL-описаний интегральных схем, страница 6

               port map(A(1)=>A,A(2)=>res1,Y=>outs);

               Y<=outs after 5ns;

end;

architecture NOAO2 of NOAO2 is

signal res1:std_logic;

signal res2:std_logic;

signal outs:std_logic;

begin

               XX_NOAO2_O2:XX

               generic map(2,op_or,pin_dir,pin_dir)

               port map(A(1)=>C,A(2)=>D,Y=>res1);

               XX_NOAO2_A2:XX

               generic map(2,op_and,pin_dir,pin_dir)

               port map(A(1)=>B,A(2)=>res1,Y=>res2);

               XX_NOAO2_NO2:XX

               generic map(2,op_or,pin_dir,pin_inv)

               port map(A(1)=>A,A(2)=>res2,Y=>outs);

               Y<=outs after 4ns;

end;

architecture O2 of O2 is

signal outs:std_logic;

begin

               XX_O2:XX

               generic map(2,op_or,pin_dir,pin_dir)

               port map(A(1)=>A,A(2)=>B,Y=>outs);

               Y<=outs after 2ns;

end;

architecture O3 of O3 is

signal outs:std_logic;

begin

               XX_O3:XX

               generic map(3,op_or,pin_dir,pin_dir)

               port map(A(1)=>A,A(2)=>B,A(3)=>C,Y=>outs);

               Y<=outs after 3ns;

end;

architecture O4 of O4 is

signal outs:std_logic;

begin

               XX_O4:XX

               generic map(4,op_or,pin_dir,pin_dir)

               port map(A(1)=>A,A(2)=>B,A(3)=>C,A(4)=>D,Y=>outs);

               Y<=outs after 4ns;

end;

architecture O6 of O6 is

signal outs:std_logic;

begin

               XX_O6:XX

               generic map(6,op_or,pin_dir,pin_dir)

               port map(A(1)=>A,A(2)=>B,A(3)=>C,A(4)=>D,A(5)=>E,A(6)=>F,Y=>outs);

               Y<=outs after 6ns;

end;

architecture O8 of O8 is

signal outs:std_logic;

begin

               XX_O6:XX

               generic map(6,op_or,pin_dir,pin_dir)

               port map(A(1)=>A,A(2)=>B,A(3)=>C,A(4)=>D,A(5)=>E,A(6)=>F,A(7)=>G,A(8)=>H,Y=>outs);

               Y<=outs after 8ns;

end;

2. Составили VHDL-модель схемы в целом.

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--

-- Title       : No Title

-- Design      : nLab_11_design

-- Author      : Buffovich

-- Company     : Adequatus

--

---------------------------------------------------------------------------------------------------

--

-- File        : F:\Workplace Buffovich\Math Models\nLab_11\nLab_11_do\nLab_11_design\compile\Schema_own.vhd

-- Generated   : Sun May 20 21:43:43 2007

-- From        : F:/Workplace Buffovich/Math Models/nLab_11/nLab_11_do/nLab_11_design/src/Schema_own.bde

-- By          : Bde2Vhdl ver. 2.6

--

---------------------------------------------------------------------------------------------------

--

-- Description :

--

---------------------------------------------------------------------------------------------------

-- Design unit header --

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity Schema_own is

  port(

       X1 : in STD_LOGIC;

       X2 : in STD_LOGIC;

       X3 : in STD_LOGIC;

       X4 : in STD_LOGIC;

       Y1 : out STD_LOGIC:='0';

       Y2 : out STD_LOGIC:='0';

       Y3 : out STD_LOGIC:='0';

       Y4 : out STD_LOGIC:='0';

       Y5 : out STD_LOGIC:='0'

  );

end Schema_own;

architecture Schema_own of Schema_own is

signal NET10587 : STD_LOGIC:='0';

signal NET10595 : STD_LOGIC:='0';

signal NET10634 : STD_LOGIC:='0';

signal NET10713 : STD_LOGIC:='0';

signal NET10744 : STD_LOGIC:='0';

signal NET10777 : STD_LOGIC:='0';

signal NET590 : STD_LOGIC:='0';

signal NET648 : STD_LOGIC:='0';

signal NET664 : STD_LOGIC:='0';

signal NET689 : STD_LOGIC:='0';

signal NET714 : STD_LOGIC:='0';

signal NET735 : STD_LOGIC:='0';

signal NET783 : STD_LOGIC:='0';

signal NET807 : STD_LOGIC:='0';

begin

----  Component instantiations  ----

U1 : N

  port map(

       A => X2,

       Y => NET689

  );

U10 : N

  port map(

       A => X4,

       Y => NET783

  );

U11 : noa2

  port map(

       A => NET714,

       B => X3,

       C => NET735,

       Y => NET10587

  );

U12 : N

  port map(

       A => NET10777,

       Y => NET10634

  );

U13 : noao2

  port map(

       A => NET783,

       B => X2,

       C => NET807,

       D => NET664,

       Y => NET10744

  );

U14 : DGND

  port map(

       Y => Y3

  );

U15 : N

  port map(

       A => NET10587,