Проектирование и моделирование VHDL-описаний интегральных схем, страница 2

                              port(A,B,C,D:in std_logic;Y:out std_logic);

               end component;

               component O2

                              port(A,B:in std_logic;Y:out std_logic);

               end component;

               component O3

                              port(A,B,C:in std_logic;Y:out std_logic);

               end component;

               component O4

                              port(A,B,C,D:in std_logic;Y:out std_logic);

               end component;

               component O6

                              port(A,B,C,D,E,F:in std_logic;Y:out std_logic);

               end component;

               component O8

                              port(A,B,C,D,E,F,G,H:in std_logic;Y:out std_logic);

               end component;

end;

package body BMC_types is

end;

--File:BMC_elements.vhd

--Содержит архитектуры и декларации объектов

library IEEE;

use IEEE.std_logic_1164.all;

entity DGND is

               port(Y:out std_logic:='0');

end;

library IEEE;

use IEEE.std_logic_1164.all;

entity VCC is

               port(Y:out std_logic:='1');

end;

library IEEE;

use IEEE.std_logic_1164.all;

entity N is

               port(A:in std_logic:='0';

               Y:out std_logic:='0');

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity XX is

               generic(input_num:integer;op:op_type;in_type,out_type:pin_type);

               port(A:in std_logic_vector(1 to input_num);

               Y:out std_logic:='0');

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity A2 is

               port(A,B:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity A3 is

               port(A,B,C:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity A4 is

               port(A,B,C,D:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity A6 is

               port(A,B,C,D,E,F:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity A8 is

               port(A,B,C,D,E,F,G,H:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity EX2 is

               port(A,B:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity MX2 is

               port(A,B,V:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity NA2 is

               port(A,B:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity NA3 is

               port(A,B,C:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity NA3O2 is

               port(A,B,C,D:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity NA4 is

               port(A,B,C,D:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity NAO2 is

               port(A,B,C:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity NAO22 is

               port(A,B,C,D:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity NAO3 is

               port(A,B,C,D:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity NAOA2 is

               port(A,B,C,D:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity NEX2 is

               port(A,B:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity NMX2 is

               port(A,B,V:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity NMX4 is

               port(A,B,C,D,V1,V2:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity NO2 is

               port(A,B:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity NO3 is