Проектирование и моделирование VHDL-описаний интегральных схем, страница 3

               port(A,B,C:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity NO3A2 is

               port(A,B,C,D:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity NO4 is

               port(A,B,C,D:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity NOA2 is

               port(A,B,C:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity NOA22 is

               port(A,B,C,D:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity NOA3 is

               port(A,B,C,D:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity NOAO2 is

               port(A,B,C,D:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity O2 is

               port(A,B:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity O3 is

               port(A,B,C:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity O4 is

               port(A,B,C,D:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity O6 is

               port(A,B,C,D,E,F:in std_logic;Y:out std_logic);

end;

library IEEE;

use IEEE.std_logic_1164.all;

use work.BMC_types.all;

entity O8 is

               port(A,B,C,D,E,F,G,H:in std_logic;Y:out std_logic);

end;

architecture DGND of DGND is

begin

end;

architecture VCC of VCC is

begin

end;

architecture N of N is

begin

               Y<=(not A) after 1ns;

end;

architecture XX of XX is

begin      

               process (A)

               variable cyc:integer;

               variable res:std_logic;

               variable rin:std_logic_vector(1 to input_num);

               begin                    

                              case in_type is

                                            when pin_dir=>rin:=A;

                                            when pin_inv=>rin:=not A;

                              end case;

                              res:=rin(1);

                              for cyc in 2 to input_num loop

                                            case op is

                                                           when op_and=>res:=res and rin(cyc);

                                                           when op_or=>res:=res or rin(cyc);

                                                           when op_xor=>res:=res xor rin(cyc);

                                            end case;

                              end loop;

                              case out_type is

                                            when pin_dir=>res:=res;

                                            when pin_inv=>res:=not res;

                              end case;

                              Y<=res;

               end process;

end;

architecture A2 of A2 is

signal outs:std_logic;

begin

               XX_A2:XX

               generic map(2,op_and,pin_dir,pin_dir)

               port map(A(1)=>A,A(2)=>B,Y=>outs);

               Y<=outs after 2ns;

end;

architecture A3 of A3 is

signal outs:std_logic;

begin

               XX_A3:XX

               generic map(3,op_and,pin_dir,pin_dir)

               port map(A(1)=>A,A(2)=>B,A(3)=>C,Y=>outs);

               Y<=outs after 3ns;

end;

architecture A4 of A4 is

signal outs:std_logic;

begin

               XX_A4:XX

               generic map(4,op_and,pin_dir,pin_dir)

               port map(A(1)=>A,A(2)=>B,A(3)=>C,A(4)=>D,Y=>outs);

               Y<=outs after 4ns;

end;

architecture A6 of A6 is

signal outs:std_logic;

begin

               XX_A6:XX

               generic map(6,op_and,pin_dir,pin_dir)

               port map(A(1)=>A,A(2)=>B,A(3)=>C,A(4)=>D,A(5)=>E,A(6)=>F,Y=>outs);

               Y<=outs after 6ns;

end;

architecture A8 of A8 is

signal outs:std_logic;

begin

               XX_A8:XX

               generic map(8,op_and,pin_dir,pin_dir)