Проектирование и моделирование VHDL-описаний интегральных схем, страница 4

               port map(A(1)=>A,A(2)=>B,A(3)=>C,A(4)=>D,A(5)=>E,A(6)=>F,A(7)=>G,A(8)=>H,Y=>outs);

               Y<=outs after 8ns;

end;

architecture EX2 of EX2 is

signal outs:std_logic;

begin

               XX_EX2:XX

               generic map(2,op_xor,pin_dir,pin_dir)

               port map(A(1)=>A,A(2)=>B,Y=>outs);

               Y<=outs after 5ns;

end;

architecture MX2 of MX2 is

signal valve1:std_logic;

signal valve2:std_logic;

signal NV:std_logic;

signal outs:std_logic;

begin

               NV<=not V;

               XX_MX2_A2_1:XX

               generic map(2,op_and,pin_dir,pin_dir)

               port map(A(1)=>A,A(2)=>NV,Y=>valve1);

               XX_MX2_A2_2:XX

               generic map(2,op_and,pin_dir,pin_dir)

               port map(A(1)=>B,A(2)=>V,Y=>valve2);

               XX_MX2_O2:XX

               generic map(2,op_or,pin_dir,pin_dir)

               port map(A(1)=>valve1,A(2)=>valve2,Y=>outs);

               Y<=outs after 3ns;

end;

architecture NA2 of NA2 is

signal outs:std_logic;

begin

               XX_NA2:XX

               generic map(2,op_and,pin_dir,pin_inv)

               port map(A(1)=>A,A(2)=>B,Y=>outs);

               Y<=outs after 2ns;

end;

architecture NA3 of NA3 is

signal outs:std_logic;

begin

               XX_NA3:XX

               generic map(3,op_and,pin_dir,pin_inv)

               port map(A(1)=>A,A(2)=>B,A(3)=>C,Y=>outs);

               Y<=outs after 3ns;

end;

architecture NA3O2 of NA3O2 is

signal res1:std_logic;

signal outs:std_logic;

begin

               XX_NA3O2_O2:XX

               generic map(2,op_or,pin_dir,pin_dir)

               port map(A(1)=>C,A(2)=>D,Y=>res1);

               XX_NA3O2_NA3:XX

               generic map(3,op_and,pin_dir,pin_inv)

               port map(A(1)=>A,A(2)=>B,A(3)=>res1,Y=>outs);

               Y<=outs after 4ns;

end;

architecture NA4 of NA4 is

signal outs:std_logic;

begin

               XX_NA4:XX

               generic map(4,op_and,pin_dir,pin_inv)

               port map(A(1)=>A,A(2)=>B,A(3)=>C,A(4)=>D,Y=>outs);

               Y<=outs after 5ns;

end;

architecture NAO2 of NAO2 is

signal res1:std_logic;

signal outs:std_logic;

begin

               XX_NAO2_O2:XX

               generic map(2,op_or,pin_dir,pin_dir)

               port map(A(1)=>B,A(2)=>C,Y=>res1);

               XX_NAO2_NA2:XX

               generic map(4,op_and,pin_dir,pin_inv)

               port map(A(1)=>A,A(2)=>res1,Y=>outs);

               Y<=outs after 3ns;

end;

architecture NAO22 of NAO22 is

signal res1:std_logic;

signal res2:std_logic;

signal outs:std_logic;

begin

               XX_NAO22_O2_1:XX

               generic map(2,op_or,pin_dir,pin_dir)

               port map(A(1)=>A,A(2)=>B,Y=>res1);

               XX_NAO22_O2_2:XX

               generic map(2,op_or,pin_dir,pin_dir)

               port map(A(1)=>C,A(2)=>D,Y=>res2);

               XX_NAO22_NA2:XX

               generic map(2,op_and,pin_dir,pin_inv)

               port map(A(1)=>res1,A(2)=>res2,Y=>outs);

               Y<=outs after 3ns;

end;

architecture NAO3 of NAO3 is

signal res1:std_logic;

signal outs:std_logic;

begin

               XX_NAO3_O3:XX

               generic map(3,op_or,pin_dir,pin_dir)

               port map(A(1)=>B,A(2)=>C,A(3)=>D,Y=>res1);

               XX_NAO3_NA2:XX

               generic map(2,op_and,pin_dir,pin_inv)

               port map(A(1)=>A,A(2)=>res1,Y=>outs);

               Y<=outs after 5ns;

end;

architecture NAOA2 of NAOA2 is

signal res1:std_logic;

signal res2:std_logic;

signal outs:std_logic;

begin

               XX_NAOA2_A2:XX

               generic map(2,op_and,pin_dir,pin_dir)

               port map(A(1)=>C,A(2)=>D,Y=>res1);

               XX_NAOA2_O2:XX

               generic map(2,op_or,pin_dir,pin_dir)

               port map(A(1)=>B,A(2)=>res1,Y=>res2);

               XX_NAOA2_NA2:XX

               generic map(2,op_and,pin_dir,pin_inv)

               port map(A(1)=>A,A(2)=>res2,Y=>outs);

               Y<=outs after 4ns;

end;

architecture NEX2 of NEX2 is

signal outs:std_logic;

begin

               XX_NEX2:XX

               generic map(2,op_xor,pin_dir,pin_inv)