Проектирование микропроцессорной системы контроля и управления объектом. Общие принципы проектирования микропроцессорных систем, страница 17

                             

        IOW                     WR                     7                       U3                 V1         X1   SW

                                                                                                                V2         X2                              

      RESET                   RES                   PC                                           V3         X3

                                                                 0              U0                         V4         X4             Y

                 ШУ                                         1                       U1                              A1           

                                                                 2                       U2                              A0

                                                                 3                                             “1”         E

                                                                 4              U4                                                                DA3 КР1408УД7

                                                                 5              U5

                                                                 6              U6

                                                                 7              U7

Рис. 3.11 Схема ввода цифровых и аналоговых сигналов

ША   DD1 КР1533ИД7                   

                                                                                      A     DC      0                   SELPT_1

                                                                             A2    0                  1                   SELPT_2

                                                                             A3    1                  2                   SELPIC

                                                                             A4    2                  3                   SELPIO

                                                                                                           4                   SELIPORT

                                                                            A5                         5        

                                                                            A6    &                  6        

                                                                            A7                         7

Рис. 3.12. Дешифратор адресов портов

                           PT_1                                                                                  PT_2

                                                            U0                                                                                  U4          &     Y2

                              PT                                                                                      PT

                                                                        &                                                                                      

  F2_ТТЛ         CLK2                                                   Y1    F2_ТТЛ        CLK0

                                    OUT2             1                                                                OUT0            1

     “1”         GATE2                                                           “1”          GATE0                                      

                                                                                                                                                                  &     Y3

 

                                                                                                                                                     U5                      

Рис. 3.13. Схема формирования сигналов Y1, Y2, Y3