Проектирование микропроцессорной системы контроля и управления объектом. Общие принципы проектирования микропроцессорных систем, страница 13

                                                                                      A    ROM                             

A0    0      16K                              

A1    1                DO                 

DD2 КР1533ЛЛ1                                          0      D0            

                      SEL                                             A10  10                   1      D1            

                                              1                                  CS1                                       

                 MEMR                                                     CS2                7      D7            

                                                           “1”                  CS3

Рис. 3.6. Подключение БИС ПЗУ со стробированием сигнала

 

ША         DD1 КР537РУ3              ША       DD8 КР537РУ3                          DD9 КР580BA86      

A     RAM                                      A    RAM                                        A      BF      B

               A0      0      4K                                 A0    0     4K                                           0        

               A1      1                                             A1    1                                                     1                   0      D0

                                             DO                                                 DO                                                    1      D1

               A11   11                                         A11   11                                                    7     

                         DI                                                   DI                                                                         7      D7

   SEL                                                                                                             “1”            TF

                         CS                                                   CS                                                   OE                                                          WE                                                 WE

                                                                                                          MEMR             

                              

 MEMW                                                                               

                  D0                                                    D7

 ШД

Рис. 3.7. ОЗУ с буферированием данных

ША   DD1 КР537РУ3                              ША    DD8 КР537РУ3                       

                                                                                     

A    RAM                                                     A    RAM

                                                A0   0       4K                                             A0    0       4K

                                                A1   1                                                         A1    1

                  DD9                                                    

MEMR                 DD11     A11   11              DO                                  A11  11              DO

                     1                                DI                                                                DI          

                                  &                  CS                                                               CS                 

 SEL                                               WE                                                              WE