Программирование на зыке VHDL: Конспект лекций, страница 12

                              DATAB : in std_logic_vector(7 downto 0);

                              RESULT : out std_logic_vector(15 downto 0)

                               );

END COMPONENT;

BEGIN

               lpm_mult_component : lpm_mult

               GENERIC MAP (

                              LPM_WIDTHA => 8,

                              LPM_WIDTHB => 8,

                              LPM_WIDTHP => 16

                              );

               PORT MAP (

                              dataa => dataa,

                              datab => datab,

                              result => result

                              );

END mult1;

Модель работает!

8.2. Примеры объявления функций LPM

8.2.1. Модель для задания в схеме сигнала константы

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

use work.LPM_COMPONENTS.all;

entity LPM_CONSTANT is

    generic (LPM_WIDTH : natural;    -- MUST be greater than 0

                                              LPM_CVALUE : natural;

                                              LPM_STRENGTH : string := "UNUSED";

                                              LPM_TYPE : string := "LPM_CONSTANT";

                                              LPM_HINT : string := "UNUSED");

               port (RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));

end LPM_CONSTANT;

architecture LPM_SYN of LPM_CONSTANT is

begin

               RESULT <= conv_std_logic_vector(LPM_CVALUE, LPM_WIDTH);

endLPM_SYN;

8.2.2. Модель для построения многоразрядного инвертора

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

use work.LPM_COMPONENTS.all;

entity LPM_INV is

               generic (LPM_WIDTH : natural;    -- MUST be greater than 0

                                             LPM_TYPE : string := "LPM_INV";

                                             LPM_HINT : string := "UNUSED");

               port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);

                                             RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0));

end LPM_INV;

architecture LPM_SYN of LPM_INV is

begin

               RESULT <= not DATA;

end LPM_SYN;

8.2.3. Модель для вычисления модуля числа

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_signed.all;

use work.LPM_COMPONENTS.all;

entity LPM_ABS is

    generic (LPM_WIDTH : natural;    -- MUST be greater than 0

                                              LPM_TYPE: string := "LPM_ABS";

                                              LPM_HINT : string := "UNUSED");

               port (DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);

                                RESULT : out std_logic_vector(LPM_WIDTH-1 downto 0);

                                OVERFLOW : out std_logic);

end LPM_ABS;

architecture LPM_SYN of LPM_ABS is

begin

               process(DATA)

               begin

                              if (DATA = -2 ** (LPM_WIDTH-1)) then

                                             OVERFLOW <= '1';

                                             RESULT <= (OTHERS => 'X');

                              elsif DATA < 0 then

                                             RESULT <= 0 - DATA;

                                             OVERFLOW <= '0';

                              else

                                             RESULT <= DATA;

                                             OVERFLOW <= '0';

                              end if;

               end process;

end LPM_SYN;

Приложение

ATTRIBUTES

<signal_name> : IN STD_LOGIC_VECTOR(7 DOWNTO 0)

• 'HIGH - 7

• 'LOW - 0

• 'RIGHT - 0

• 'LEFT - 7

• 'RANGE - 7 DOWNTO 0

• 'REVERSE RANGE - 0 TO 7

• 'LENGTH - 8

SUBPROGRAMS

• FUNCTIONS

• PROCEDURES

SUBPROGRAMS

FUNCTIONS

• Format:

FUNCTIONS

• For functions:

- only allowable mode for parameters is in