Программирование на зыке VHDL: Конспект лекций, страница 13

- only allowed object classes are constant or signal

- if the object class is not specified, constant is assumed

PROCEDURES

• Format:

PROCEDURES

• For Procedures:

- allowable modes for parameters are in, out, and inout

- allowable object classes for parameters are constant, variable and signal

- If the mode is in and no object class is specified, then constant is assumed.

- If the mode is inout or out and if no object class is specified, then variable is assumed.

Signal Assignment inside a Process – delay

2 Process    vs.             1 Process

Variable Assignment • no delay

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Литература

1.  Ф.С.Шапо, В.Ф.Шапо. Введение в VHDL —язык проектирования цифровых систем. — Одесса, Астропринт 2001.

2.  П.Н.Бибило. Основы языка VHDL.— М., “Солон-Р”, 2000

3.  Sudhakar Yalamanchili. Introdactionary VHDL. From Simulation to Synthesis. Prenciple Hall, Upper Saddle River, New Jersey 07458. 2001

4.  M.Morris Mano, Charles R.Kime. Logic and Computer Design Fundamentals, Second Edition Updated. Prenciple Hall, Upper Saddle River, New Jersey 07458. 2001

5.  Zoran Salcic. VHDL and FPLDs in Digital Systems Design, Prototyping and Customization. Kluwer Academic Publishers. Boston/Dordrecht/London, 1998

6.  Allen M. Deway. Analysis and Design of Digital Systems with VHDL. PWS Publishing Company. 1997

7.  John F. Wakerly. Digital Design: Principles and Practices, Third Edition. Prenciple Hall, Upper Saddle River, New Jersey 07458. 2000

Содержание

Введение.................................................................................................................................... 2

Задачи курса........................................................................................................................... 2

Содержание курса.................................................................................................................. 2

1. Основы VHDL........................................................................................................................ 2

1.1. Происхождение термина VHDL:...................................................................................... 2

1.2. Что такое VHDL?............................................................................................................. 3

1.3. История VHDL................................................................................................................ 3

1.4. Терминология.................................................................................................................. 3

1.5. Behavior Modeling - моделирование поведения................................................................ 3

1.6. Structural Modeling - моделирование структуры.............................................................. 3

1.7. Еще о терминологии........................................................................................................ 4

1.8. Особенности синтеза RTL............................................................................................... 4

1.9. Сравнение методики синтеза схем VHDL с другими стандартами HDL.......................... 4

1.10. Typical Synthesis Design Flow – Порядок синтеза схемы................................................ 5

1.11. Typical Simulation Design Flow – Порядок моделирования схемы.................................. 6