Программирование на зыке VHDL: Конспект лекций, страница 11

Name	Description
Gates
lpm_and	Multi-bit and gate for bit-wise and operation
lpm_bustri	Multi-bit three-state buffer for unidirectional and bidirectional buffer implementation
lpm_clshift	Combinatorial Logic Shifter or Barrel Shifter
Lpm_constant	Constant Generator
lpm_decode	Decoder
lpm_or	Multi-bit or gate for bit-wise or operation
lpm_xor	Multi-bit xor gate for bit-wise xor operation
lpm_inv	Multi-bit inverter
Busmux	Two-input multi-bit multiplexer (can be derived from lpm_mux)
lpm_mux	Multi-input multi-bit multilexer
Mux	Single input multi-bit multiplexer (can be derived from lpm_mux)
Arithmetic Components
lpm_abs	Absolute value
lpm_add_sub	Multi-bit Adder/Subtractor
lpm_compare	Two-input multi-bit comparator
lpm_counter	Multi-bit counter with various control options
lpm_mult	Multi-bit multiplier
Memory Components
lpm_ram_dq		Synchronous or asynchronous RAM with separate input and output ports
1pm_ram_io		Synchronous or asynchronous RAM with a single I/O port
1pm_rom		Synchronous or asynchronous ROM
Csdpram		Cycle-shared dual-port RAM
Csfifo		Cycle-shared first-in first-out (FIFO) buffer

Удобно использовать мастер построения VHDL-моделей на базе модулей LPM, входящий в состав программного пакета MAX+ PLUS II корпорации Altera.

8.1. Пример использования функции LPM_MULT

В библиотеке LPM имеется описание компонента для выполнения операций перемножения целых чисел:

entity LPM_MULT is

    generic (LPM_WIDTHA : natural;    -- MUST be greater than 0

             LPM_WIDTHB : natural;    -- MUST be greater than 0

                                              LPM_WIDTHS : natural := 0;

             LPM_WIDTHP : natural;    -- MUST be greater than 0

                                              LPM_REPRESENTATION : string := "UNSIGNED";

             LPM_PIPELINE : natural := 0;

                                              LPM_TYPE: string := "LPM_MULT";

                                              LPM_HINT : string := "UNUSED");

               port (DATAA : in std_logic_vector(LPM_WIDTHA-1 downto 0);

                                DATAB : in std_logic_vector(LPM_WIDTHB-1 downto 0);

                                ACLR : in std_logic := '0';

                                CLOCK : in std_logic := '0';

                                CLKEN : in std_logic := '1';

                                SUM : in std_logic_vector(LPM_WIDTHS-1 downto 0) := (OTHERS => '0');

                                RESULT : out std_logic_vector(LPM_WIDTHP-1 downto 0));

endLPM_MULT;

Создадим на его основе узел для перемножения двух 8-разрядных чисел:

library IEEE;

library LPM;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use LPM.LPM_COMPONENTS.all;

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY mult IS

               PORT

               (

                              dataa                    : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

                              datab                    : IN STD_LOGIC_VECTOR (7 DOWNTO 0);

                              result                   : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)

               );

END mult;

ARCHITECTURE mult1 OF mult IS

COMPONENT lpm_mult

               generic (LPM_WIDTHA : natural;    -- MUST be greater than 0

               LPM_WIDTHB : natural;    -- MUST be greater than 0

               LPM_WIDTHP : natural);    -- MUST be greater than 0

               port (DATAA : in std_logic_vector(7 downto 0);