Программирование на зыке VHDL: Конспект лекций, страница 10

libraryIEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

entity StM1 is

               port (

                              A: in STD_LOGIC;

                              B: in STD_LOGIC;

                              CLOCK: in STD_LOGIC;

                              RESET: in STD_LOGIC;

DETECTED: out  STD_LOGIC);

end;

architecture StM1 of StM1 is

type Sreg0_type is (Start, StateB, StateA);

signal Sreg0: Sreg0_type;

begin

               Sreg0_machine: process (CLOCK)          

               begin

                              if RESET = '1' then

                                             Sreg0 <= Start;

                              else if CLOCK'event and CLOCK = '1' then

                                             case Sreg0 is

                                                            when Start =>

                                                                           if A='1' then

                                                                                          Sreg0 <= StateA;

                                                                           end if;

                                                            when StateB =>

                                                                           if A='0' and B='0' then

                                                                                          Sreg0 <= Start;

                                                                           elsif B='1' then

                                                                                          Sreg0 <= StateB;

                                                                           elsif A='1' and  B='0' then

                                                                                          Sreg0 <= StateA;

                                                                           end if;

                                                            when StateA =>

                                                                           if B='0' then

                                                                                          Sreg0 <= StateA;

                                                                           elsif A='1' and B='1' then

                                                                                          Sreg0 <= StateB;

                                                                           elsif A='0' then

                                                                                          Sreg0 <= Start;

                                                                           end if;

                                                            when others =>

                                                                           null;

                                             end case;

                              end if;

               end process;

DETECTED_assignment:

DETECTED <=                '1' when (Sreg0 = StateB) else

'0' when (Sreg0 = StateA) else 

'0';

endStM1;

7.1.2.2. Другой пример конечного автомата. Перечислимый тип данных - Enumerated Data Type

7.1.2.3. Переключение состояний автомата - Next State Logic

7.1.2.4. Формирование выходных сигналов - Outputs

7.1.2.5. Формирование выходных сигналов с использованием оператора Case

8. Функции LPM

В библиотеке LPM определены следующие компоненты: