Моделирование цифровых устройств с использованием пакета VHDL. Логический элемент К155ЛА2. Моделирование элементов схемы, страница 5

--  created by Design Wizard: 05/18/03 19:44:45

-library IEEE;

use IEEE.std_logic_1164.all;

entity k155tm2 is

port (

r_1: in STD_LOGIC;

c_1: in STD_LOGIC;

d_1: in STD_LOGIC;

s_1: in STD_LOGIC;

q_1: out STD_LOGIC;

q_1n: out STD_LOGIC

);

end k155tm2;

architecture k155tm2 of k155tm2 is

begin

-- <<enter your statements here>>

process(r_1,c_1,s_1,d_1)

begin

if s_1='0' and r_1='1' then

q_1<='1' after 35 ns;

q_1n<='0' after 35 ns;

end if;

if s_1='1' and r_1='0' then

q_1<='0' after 35 ns;

q_1n<='1' after 35 ns;

end if;

if s_1='0' and r_1='0' then

q_1<='1' after 35 ns;

q_1n<='1' after 35 ns;

end if;

if c_1'event and c_1='1' and s_1='1' and r_1='1' then

q_1<=d_1 after 35 ns;

q_1n<=not d_1 after 35 ns;

end if;

end process;

end k155tm2;

Модельэлемента К559ИП2

---  File: k559ip2.vhd

--  created by Design Wizard: 05/18/03 20:02:50

-library IEEE;

use IEEE.std_logic_1164.all;

entity k559ip2 is

port (

l1: in STD_LOGIC;

l2: in STD_LOGIC;

t: out STD_LOGIC

);

end k559ip2;

architecture k559ip2 of k559ip2 is

begin

-- <<enter your statements here>>

process(l1,l2)

begin

t<=l1 or l2 after 10 ns;

end process;

end k559ip2;

Модельэлемента К589АП26

---  File: k589ap26.vhd

--  created by Design Wizard: 05/18/03 20:12:53

-library IEEE;

use IEEE.std_logic_1164.all;

entity k589ap26 is

port (

dce: in STD_LOGIC;

cs: in STD_LOGIC;

di0: in STD_LOGIC;

di1: in STD_LOGIC;

di2: in STD_LOGIC;

di3: in STD_LOGIC;

db0: inout STD_LOGIC;

db1: inout STD_LOGIC;

db2: inout STD_LOGIC;

db3: inout STD_LOGIC;

d00: out STD_LOGIC;

d01: out STD_LOGIC;

d02: out STD_LOGIC;

d03: out STD_LOGIC

);

end k589ap26;

architecture k589ap26 of k589ap26 is

begin

-- <<enter your statements here>>

process(dce,cs,di0,di1,di2,di3,db0,db1,db2,db3)

begin

if dce='0' and cs='0'then

db0<= not di0 after 25 ns;

db1<= not di1 after 25 ns;

db2<= not di2 after 25 ns;

db3<= not di3 after 25 ns;

end if;

if dce='1' and cs='0'then        

d00<= not db0 after 25 ns;

d01<= not db1 after 25 ns;

d02<= not db2 after 25 ns;

d03<= not db3 after 25 ns;

end if;

if dce='1' and cs='1' then

d00<='Z' after 25 ns;

d01<='Z' after 25 ns;

d02<='Z' after 25 ns;

d03<='Z' after 25 ns;

end if;

end process;        

end k589ap26;

Модель элемента К599ИП1

---  File: k599ip1.vhd

--  created by Design Wizard: 05/18/03 20:27:14

-library IEEE;

use IEEE.std_logic_1164.all;

entity k599ip1 is

port (

f1: in STD_LOGIC;

f2: in STD_LOGIC;

t1: out STD_LOGIC

);

end k599ip1;

architecture k599ip1 of k599ip1 is

begin

-- <<enter your statements here>>

process(f1,f2)

begin

t1<=f1 and f2 after 10 ns;

end process;

end k599ip1;

                                         3.2. Моделирование  схемы.

library IEEE;

use IEEE.std_logic_1164.all;

entity top is

port(

k1: in std_logic;

k2: in std_logic;

k3: in std_logic;

k4: in std_logic;

k5: in std_logic;

k6: inout std_logic;

k7: inout std_logic;

k8: inout std_logic;

k9: inout std_logic;

k10: inout std_logic;

k11: inout std_logic;

k12: inout std_logic;

k13: inout std_logic;

k14: inout std_logic;

k15: inout std_logic;

k16: inout std_logic;

k17: inout std_logic;

k18: in std_logic;

k19: in std_logic;

s59,s60,s61,s62,s67,s68,s69,s70,s74,s75,s76,s77:in std_logic;

z1: out std_logic;

z2: out std_logic;

z3: out std_logic;

z4: out std_logic;

z5: out std_logic;

z6: out std_logic;

z7: out std_logic;

z8: out std_logic;

z9: out std_logic;

z10: out std_logic;

z11: out std_logic;

z12: out std_logic;

z13: out std_logic;

z14: out std_logic

);

end top;

architecture structure of top is

component k155la2 is

port (

x1: in STD_LOGIC;

x2: in STD_LOGIC;

x3: in STD_LOGIC;

x4: in STD_LOGIC;

x5: in STD_LOGIC;

x6: in STD_LOGIC;

x7: in STD_LOGIC;

x8: in STD_LOGIC;

y1: out STD_LOGIC

);

end component;

component k155la3 is

port (

c1: in STD_LOGIC;

c2: in STD_LOGIC;

y2: out STD_LOGIC

);

end component;

component k155la6 is

port (

a1: in STD_LOGIC;

a2: in STD_LOGIC;

a3: in STD_LOGIC;

a4: in STD_LOGIC;

y3: out STD_LOGIC

);

end component;

component k155le1 is