-- created by Design Wizard: 05/18/03 18:44:56
-library IEEE;
use IEEE.std_logic_1164.all;
entity k155la2 is
port (
x1: in STD_LOGIC;
x2: in STD_LOGIC;
x3: in STD_LOGIC;
x4: in STD_LOGIC;
x5: in STD_LOGIC;
x6: in STD_LOGIC;
x7: in STD_LOGIC;
x8: in STD_LOGIC;
y1: out STD_LOGIC
);
end k155la2;
architecture k155la2 of k155la2 is
begin
process(x1,x2,x3,x4,x5,x6,x7,x8)
begin
y1<=not(x1 and x2 and x3 and x4 and x5 and x6 and x7 and x8)after 22 ns;
end process;
end k155la2;
Модель элемента К155ЛА3
- File: k155la3.vhd
-- created by Design Wizard: 05/18/03 18:50:59
-library IEEE;
use IEEE.std_logic_1164.all;
entity k155la3 is
port (
c1: in STD_LOGIC;
c2: in STD_LOGIC;
y2: out STD_LOGIC
);
end k155la3;
architecture k155la3 of k155la3 is
begin
-- <<enter your statements here>>
process (c1,c2)
begin
y2<= c1 nand c2 after 22 ns;
end process;
end k155la3;
Модель элемента К155ЛА6
- File: k155la6.vhd
-- created by Design Wizard: 05/18/03 18:54:56
-library IEEE;
use IEEE.std_logic_1164.all;
entity k155la6 is
port (
a1: in STD_LOGIC;
a2: in STD_LOGIC;
a3: in STD_LOGIC;
a4: in STD_LOGIC;
y3: out STD_LOGIC
);
end k155la6;
architecture k155la6 of k155la6 is
begin
-- <<enter your statements here>>
process(a1,a2,a3,a4)
begin
y3<=not(a1 and a2 and a3 and a4) after 22 ns;
end process;
end k155la6;
Модель элемента К155ЛЕ1
- File: k155le1.vhd
-- created by Design Wizard: 05/18/03 18:58:11
-library IEEE;
use IEEE.std_logic_1164.all;
entity k155le1 is
port (
d1: in STD_LOGIC;
d2: in STD_LOGIC;
y4: out STD_LOGIC
);
end k155le1;
architecture k155le1 of k155le1 is
begin
-- <<enter your statements here>>
process(d1,d2)
begin
y4<=not(d1 or d2)after 15 ns;
end process;
end k155le1;
Модель элемента К155РУ2
--- File: k155ru2.vhd
-- created by Design Wizard: 05/18/03 19:02:17
-library IEEE;
use IEEE.std_logic_1164.all;
entity k155ru2 is
port (
aa1: in STD_LOGIC;
aa2: in STD_LOGIC;
aa3: in STD_LOGIC;
aa4: in STD_LOGIC;
cs: in STD_LOGIC;
w: in STD_LOGIC;
dd1: in STD_LOGIC;
dd2: in STD_LOGIC;
dd3: in STD_LOGIC;
dd4: in STD_LOGIC;
qq1: out STD_LOGIC;
qq2: out STD_LOGIC;
qq3: out STD_LOGIC;
qq4: out STD_LOGIC
);
end k155ru2;
architecture k155ru2 of k155ru2 is
begin
-- <<enter your statements here>>
process(aa1,aa2,aa3,aa4,cs,w,dd1,dd2,dd3,dd4)
type sit is array(0 to 15, 1 to 4) of std_logic;
variable nt,aaa1,aaa2,aaa3,aaa4: integer;
variable mas: sit;
begin
aaa1:=0;
aaa2:=0;
aaa3:=0;
aaa4:=0;
if aa1='1' then aaa1:=1; end if;
if aa2='1' then aaa2:=1; end if;
if aa3='1' then aaa3:=1; end if;
if aa4='1' then aaa4:=1; end if;
nt:=1*aaa1+2*aaa2+4*aaa3+8*aaa4;
if cs='0' and w='0'then
mas(nt,1):=dd1;
mas(nt,2):=dd2;
mas(nt,3):=dd3;
mas(nt,4):=dd4;
end if;
if cs='0' and w='1'then
qq1<=not mas(nt,1) after 50 ns;
qq2<=not mas(nt,2) after 50 ns;
qq3<=not mas(nt,3) after 50 ns;
qq4<=not mas(nt,4) after 50 ns;
end if;
end process;
end k155ru2;
Модель элемента К155ТМ8
-
-- File: k155tm8.vhd
-- created by Design Wizard: 05/18/03 19:24:14
-library IEEE;
use IEEE.std_logic_1164.all;
entity k155tm8 is
port (
r: in STD_LOGIC;
c: in STD_LOGIC;
d5_0: in STD_LOGIC;
d5_1: in STD_LOGIC;
d5_2: in STD_LOGIC;
d5_3: in STD_LOGIC;
q5_0n: out STD_LOGIC;
q5_0: out STD_LOGIC;
q5_1n: out STD_LOGIC;
q5_1: out STD_LOGIC;
q5_2n: out STD_LOGIC;
q5_2: out STD_LOGIC;
q5_3n: out STD_LOGIC;
q5_3: out STD_LOGIC
);
end k155tm8;
architecture k155tm8 of k155tm8 is
begin
-- <<enter your statements here>>
process(r,c,d5_0,d5_1,d5_2,d5_3)
variable q51,q50,q52,q53: std_logic;
begin
if r='0'then
q50:='0';
q51:='0';
q52:='0';
q53:='0';
else
if c'event and c='1' then
q50:=d5_0;
q51:=d5_1;
q52:=d5_2;
q53:=d5_3;
end if;
end if;
q5_0<=q50 after 35 ns;
q5_1<=q51 after 35 ns;
q5_2<=q52 after 35 ns;
q5_3<=q53 after 35 ns;
q5_0n<= not q50 after 35 ns;
q5_1n<= not q51 after 35 ns;
q5_2n<= not q52 after 35 ns;
q5_3n<= not q53 after 35 ns;
end process;
end k155tm8;
Модельэлемента К155ТМ2
--- File: k155tm2.vhd
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