In 5V and 3.3V PCI applications the ADSP-2192 2.5V IVDD supply will be generated by an on-chip regulator. The internal 2.5V supply (IVDD) can be generated by the on-chip regulator combined with an external power transistor as shown in Figure 11-4 on page 11-27. To support the PCI specification’s power down modes, the two transistors control the primary and auxiliary supply. If the reference voltage on RVDD (typically the same as PCIVDD) drops out, the VCTRLAUX will switch on the device connected to PCIVAUX and VCTRLVDD will switch off the primary supply. USB applications may require an external high-efficiency switching regulator to generate the 2.5V supply for the ADSP-2192.
Figure 11-4. ADSP-2192 2.5V Regulator Options
The ADSP-2192 supports several hardware and software states with distinct power management and functionality capabilities.
The driver and DSP code take responsibility for detailed power management of the modem, so minimum power levels are achieved regardless of OS or BIOS. The driver and DSPs manage power by changing platform states as necessary in response to events.
Each DSP can be in one of several power management states. A DSP can be running, in idle mode with memory clocks running, in idle mode with memory clocks stopped, or powered down. If everything else on the chip is powered down, the crystal can be running or not running.
In addition to the power management states of each DSP, the ADSP-2192 interfaces each have their own power management states. These states are not totally dependent on the hardware but are controlled by the driver software and can be changed to reduce overall power on the chip. The PCI interface supports the following power management states: D0, D1, D2, D3hot, and D3cold. The USB can be running, reset, or suspended. The AC’97 codecs can be powered up or powered down. Additionally, they have power management options to power down only DACs or ADCs, or to power down the link.
In addition to supporting powerdown modes for the PCI, USB, and AC’97 standards, the ADSP-2192 supports additional powerdown modes for the DSP cores and peripheral buses. The powerdown modes are controlled by the DSP1 and DSP2 Interrupt/Powerdown registers.
The ADSP-2192 processor provides a powerdown feature that allows the processor to enter a very low power dormant state through hardware or software control. (Refer to the processor data sheet for exact power consumption specifications.)
The powerdown feature is useful for applications where power conservation is necessary (for example in battery-powered operation).
The powerdown feature has the following effects:
• Internal clocks are disabled
• Processor registers and memory contents are maintained
• The chip can recover from powerdown in less than 100 XTALI cycles • The chip can disable internal oscillator when using crystal
• Processor does not need to shut down clock for lowest power when using external oscillator
• Interrupt support enables “housekeeping” code to execute before entering powerdown and after recovering from powerdown
• User-selectable powerup context is provided
Even though the processor is put into the powerdown mode, the lowest level of power consumption still might not be achieved if certain guidelines are not followed. Lowest possible power consumption requires no additional current flow through processor output pins and no switching activity on active input pins. Therefore, a careful analysis of pin loading in the circuit is required.
The following sections detail the proper powerdown procedure and provide guidelines for clock and output pin connections required for optimum low-power performance. Refer to “AC’97 Codec Port” on page 9-1 for more information about powering the ADSP-2192 up or down through the AC’97 interface, or to “Host (PCI/USB) Port” on page 8-1 for more information about doing this through the USB or PCI interfaces.
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