Sources for Additiona l Information. Emulator Pin Descriptions (Continued). Clock Signals. Mechanism for booting on the ADSP-2192, страница 7

Register Name	Value Changed after Reset or Software Reboot?	New Value
B4	no	unchanged
B5	no	unchanged
B6	no	unchanged
B7	no	unchanged
SYSCTL	no	unchanged
DMAPAGE	no	unchanged
CACTL	yes	0
STCTL0	no	unchanged
SRCTL0	no	unchanged
TX0	no	unchanged
RX0	no	unchanged
STCTL1	no	unchanged
SRCTL1	no	unchanged
TX1	no	unchanged
RX1	no	unchanged
TPERIOD	no	unchanged
TCOUNT	no	unchanged
TSCALE	no	unchanged

Inte rrupts

Register Name	Value Changed after Reset or Software Reboot?	New Value
TSCALECNT	no	unchanged
FLAGS	yes	0

Inte rrup ts

See “ADSP-2192 Interrupts” on page E-1 for information about interrupts on the ADSP-2192.

Fla g Pins

The ADSP-2192 processor has eight dedicated general-purpose flag pins, IO0-7. These flags can be programmed as either inputs or outputs; they default to inputs following reset. The IOx pins are programmed with the use of two memory-mapped registers. The value of the GPIO configuration register determines the flag direction: 0=output and 1=input. The Programmable Flag Data register is used to read and write the values on the pins. (Refer to “ADSP-2192 DSP Peripheral Registers” on page B-1 and “Setting Dual DSP Core Features” on page 6-3 for more information about these registers.)

Data being read from a pin configured as an input is synchronized to the processor’s clock. Pins configured as outputs drive the appropriate output value. When the GPIO status register is read, any pins configured as outputs will read back the value being driven out; the status is “sticky”; writing a zero clears it, but writing a one has no effect.

Powe rup a nd Powe rd own

This section discusses all possible power states on the ADSP-2192, including the PCI, USB, and AC’97 peripheral interfaces.

The power states of the two DSPs are independent of each other. Each DSP can be in one of the following states: running, in idle with memory clocks running, in idle with memory clocks stopped, or completely powered down.

Each AC’97 codec can be powered up, powered down, or in one of several power levels in between (including DACs only powered down, ADCs only powered down, or the entire link powered down). See “AC’97 Codec Port” on page 9-1 for more information about AC’97 and its power states.

The PCI interface supports the following PCI power management states:

D0, D1, D2, D3hot, and D3cold. See “Host (PCI/USB) Port” on page 8-1 for more information about PCI and its power management states.

The USB interface supports the following power management states: running, reset, or suspended. See “Host (PCI/USB) Port” on page 8-1 for more information about USB and its power management sates.

If everything else on the ADSP-2192 is powered down, the clock crystal can either be running or stopped.

See “Power Management Description” on page 11-28 for more information about power issues on the ADSP-2192.

Powe rup Issue s