Sources for Additiona l Information. Emulator Pin Descriptions (Continued). Clock Signals. Mechanism for booting on the ADSP-2192, страница 12

If PORST (power on reset) is asserted while the processor is in the powerdown mode, the processor is reset and instructions are executed from address 0x10000. A boot is performed if the boot mode is set. If the PORST pin is used to exit powerdown, it must be held low for the appropriate number of cycles. If the clock is stopped at powerup or is operating at a different frequency at powerup than it was before powerdown, PORST must be held long enough for the oscillator to stabilize, plus an additional 1000 XTALI cycles for the phase locked loop (PLL) to lock. The time required for the oscillator to stabilize depends upon the type of crystal used and capacitance of the external crystal circuit. Typically 2000 XTALI cycles is adequate for clock stabilization time.

If the clock was not stopped at powerup and is at a stable frequency at powerup (same as before powerdown), only 5 cycles of PORST are required.

Sta rtup Time a fter Powerdown

The time required to exit the powerdown state depends on whether an internal or external oscillator is used, and the method used to exit powerdown.

Using a n Exte rna l TTL/C MO S C loc k

When in PCI or CardBus mode, the external clock signal is ignored if both DSPs and the AC’97 link are powered down and the XON (Xtal Force On) bit in the CMSR register has not been set. When in USB mode, the USB interface must also be suspended for the clock to be ignored. In Sub-ISA mode, the clock must remain running.

The external clock is ignored internally; you do not need to stop it, since no power is wasted while it is running. Since the PCI and USB interfaces can restart the ADSP-2192 without warning, we recommend that the external clock remain running as long as there is power in the system.

Proc essor O pera tion During Powerdo wn

Some processor circuitry may still be active during powerdown mode. Also, some output pins remain active. A good understanding of these states will allow you to determine the best low-power configuration for your system. By keeping output loading and input switching to a minimum, the lowest possible power consumption can be achieved.

Inte rrup ts A nd Fla g s

DSP interrupts are latched and will be serviced when the processor exits powerdown. Any activity on the flag input pins during a low power state may increase the power consumption. There should also be no resistive load on the flag output pins (as with any active output pin) if lowest power is desired.

C onditions for Lowest Power C onsumption

All pins on the ADSP-2192 remain active as long as power is maintained to the chip. This chip does not have a specifically-defined powerdown state; at any time either or both of the two processors can be in a low power state, and any or all of the interfaces can be in a low power state. Because of this wide variety of power state options, each interface (and its associated pins) must follow a bus standard power state specific to that interface. Each interface is maintained in a power state as defined by the standard for that interface.

To assure the lowest power consumption, all active input pins should be held at a CMOS level (to ground level, if possible). All active output pins should be free of resistive load, since load current increases power dissipation. You must perform a careful analysis of each input and output pin in order to ensure the lowest power dissipation.

Some inputs are active but are ignored. The state of these inputs does not matter as long as they are at a CMOS level.

Additionally, each peripheral interface (USB, PCI, and AC’97) can be put into a low power mode, as described in the following sections.

A C ’97 Low Powe r Mod e

The AC’97 link is powered down or is put into a low power state by commands issued to the external AC’97 codec. The AC’97 link can be in a cold powerdown state or a warm powerdown state. In the cold powerdown state, ACRST is asserted, and BITCLK and SYNC are halted. In the warm powerdown state, BITCLK and SYNC are also halted, but ACRST is deasserted.