Design Note DN-8. Application Circuits. The circuit descriptions below assume some familiarity with the functioning of TOPSwitch, страница 5

∆V_OUT = 180mV × = 36mV

This translates to a variation of 0.7% over the range of duty cycle.  This variation in voltage drop with duty cycle, as well as changes to the average value of the bias voltage due to duty cycle changes, gives rise to the variation in output voltage with input line voltage observed in Figure 4.

D

12/95

Output Filter Components

In each of the circuits shown in this Design Note, the output voltage is filtered with a π-network consisting of C2, C3, and L1.  C2 is chosen for low ESR and high ripple current capability. The RMS output ripple current carried by C2 is approximately equal to the DC output current in amperes, and the capacitor should be chosen accordingly.  A second stage filter is necessary to reduce the 100 kHz and high frequency ripple and noise to 50 mV.  Without the second stage of the filter, the fundamental switching component exceeds 100 mV at maximum load, with high frequency spike noise of several hundred millivolts.  The inductor used for L1 is not critical.  Any inductor of  0.5 to 2 µH with sufficient current capability will work.  In the original prototype, both a small ferrite bead on a wire lead with an inductance of 1 µH, and 0.5 µH air-core inductor were tried with virtually identical results.  For higher output powers, the ferrite bead would be unsuitable due to saturation.

An electrolytic capacitor is the best choice for C3.  This choice is dictated both by cost and damping considerations.  The original circuit utilized a 0.1 µF ceramic capacitor in the second-stage filter.  This choice turned out to be unsuitable due to the high Q of the ceramic capacitor, which resulted in high frequency, lightly damped ringing at the output of the supply. Electrolytic capacitors have sufficient ESR to damp the resonance with the filter inductor.

The value of filter capacitors will have an effect on the stability of the supply, as they roll off the gain of the bias voltage control loop.  Insufficient output capacitance will cause the bias regulation loop to oscillate.  Stability of the supply can be checked by step loading the bias supply with a pulsed load of around 5 mA and checking the response at the bias filter capacitor (C5 in Figure 1 and C4 in Figure 2).

NOTES

D

12/95