Дешифратор адреса УПП-50. Логический элемент «8И-НЕ» К155ЛА2. Код VHDL. Waveform схемы, страница 3

port (

input1: in STD_LOGIC;

input2: in STD_LOGIC;

input3: in STD_LOGIC;

input4: in STD_LOGIC;

input5: in STD_LOGIC;

input6: in STD_LOGIC;

input7: in STD_LOGIC;

input8: in STD_LOGIC;

output_inv: out STD_LOGIC

);

end k155la2;

architecture k155la2 of k155la2 is

begin

output_inv<= transport not (input1 and input2 and input3 and input4 and input5 and input6 and input7 and input8) after 27ns;

-- <<enter your statements here>>

end k155la2;

k559ip2p.VHD

library IEEE;

use IEEE.std_logic_1164.all;

entity k559ip2p is

port (

input1: in STD_LOGIC;

input2: in STD_LOGIC;

output_inv: out STD_LOGIC

);

end k559ip2p;

architecture k559ip2p of k559ip2p is

begin

output_inv <= transport not (input1 or input2) after 20ns;

-- <<enter your statements here>>

end k559ip2p;

top.vhd

library IEEE;

use IEEE.std_logic_1164.all;

entity top is

port (

da_in_bus: in STD_LOGIC_VECTOR (12 downto 1);

sia: in STD_LOGIC;

vu: in STD_LOGIC;

bus1_port7: in STD_LOGIC;

da_out_bus: out STD_LOGIC_VECTOR (2 downto 1);

adb: out STD_LOGIC;

rpz: out STD_LOGIC;

vm_bus: out STD_LOGIC_VECTOR (7 downto 0);

rpz_bus: out STD_LOGIC_VECTOR (6 downto 1)

);

end top;

architecture top of top is

component k155re3_2 is

port (

a: in STD_LOGIC_VECTOR (7 downto 0);

en_inv: in STD_LOGIC;

q: out STD_LOGIC_VECTOR (7 downto 0)

);

end component;

component k559ip2p is

port (

input1: in STD_LOGIC;

input2: in STD_LOGIC;

output_inv: out STD_LOGIC

);

end component;

component k589ap16 is

port (

d1: in STD_LOGIC_VECTOR (3 downto 0);

db: inout STD_LOGIC_VECTOR (3 downto 0);

dce: in STD_LOGIC;

cs_inv: in STD_LOGIC;

d0: out STD_LOGIC_VECTOR (3 downto 0)

);

end component;

component k155la2 is

port (

input1: in STD_LOGIC;

input2: in STD_LOGIC;

input3: in STD_LOGIC;

input4: in STD_LOGIC;

input5: in STD_LOGIC;

input6: in STD_LOGIC;

input7: in STD_LOGIC;

input8: in STD_LOGIC;

output_inv: out STD_LOGIC

);

end component;

component k155tm7 is

port (

d1: in STD_LOGIC;

d2: in STD_LOGIC;

d3: in STD_LOGIC;

d4: in STD_LOGIC;

q1: out STD_LOGIC;

q2: out STD_LOGIC;

q3: out STD_LOGIC;

q4: out STD_LOGIC;

q1_inv: out STD_LOGIC;

q2_inv: out STD_LOGIC;

q3_inv: out STD_LOGIC;

q4_inv: out STD_LOGIC;

c1: in STD_LOGIC;

c2: in STD_LOGIC

);

end component;

component k155re3_1 is

port (

a: in STD_LOGIC_VECTOR (7 downto 0);

en_inv: in STD_LOGIC;

q: out STD_LOGIC_VECTOR (7 downto 0)

);

end component;

signal s1,s2,s3,s4,s5,s6,s7,s8: STD_LOGIC;

signal d8_in_bus: STD_LOGIC_VECTOR(7 downto 0);

signal d9_in_bus: STD_LOGIC_VECTOR(7 downto 0);

signal d9_out_bus: STD_LOGIC_VECTOR(7 downto 0);

signal one,zero:STD_LOGIC;

signal bus1:STD_LOGIC_VECTOR(7 downto 1);

signal bus2:STD_LOGIC_VECTOR(14 downto 1);

begin

one<='1';

zero<='0';

d13:k559ip2p port map (input1=>da_in_bus(2),

input2=>da_in_bus(2),

output_inv=>s1);

d12:k559ip2p port map (input1=>da_in_bus(3),

input2=>da_in_bus(3),

output_inv=>s2);

d11:k559ip2p port map (input1=>da_in_bus(1),

input2=>da_in_bus(1),

output_inv=>s3);

d21:k559ip2p port map (input1=>vu,

input2=>da_in_bus(12),

output_inv=>s4);

d22:k559ip2p port map (input1=>da_in_bus(11),

input2=>da_in_bus(10),

output_inv=>s5);

d23:k559ip2p port map (input1=>da_in_bus(8),

input2=>da_in_bus(7),

output_inv=>s6);

d24:k559ip2p port map (input1=>da_in_bus(6),

input2=>da_in_bus(6),

output_inv=>s7);

d4:k155la2 port map (input1=>s4,

input2=>s5,

input3=>s5,

input4=>s5,

input5=>s6,

input6=>s6,

input7=>s7,

input8=>da_in_bus(9),

output_inv=>s8);

d6: k155tm7 port map (d1=>s1,

d2=>s2,

d3=>s3,

d4=>'X',

c1=>sia,

c2=>sia,

q1=>bus1(2),

q2=>bus1(3),

q3=>bus1(1));

d7: k155tm7 port map (d1=>s8,

d2=>da_in_bus(5),

d3=>da_in_bus(4),

d4=>'X',

c1=>sia,

c2=>sia,

q1=>bus1(6),

q2=>bus1(5),

q3=>bus1(4));

bus1(7)<=bus1_port7;

d8_in_bus<="XXX"&bus1(6)&bus1(2)&bus1(5)&bus1(4)&bus1(3);

d8:k155re3_1 port map (a=>d8_in_bus,

en_inv=>zero,

q=>bus2(8 downto 1));

d9_in_bus<="XXX"&bus1(6)&bus1(7)&bus1(5)&bus1(4)&bus1(3);

d9:k155re3_2 port map (a=>d9_in_bus,

en_inv=>zero,

q=>d9_out_bus);

bus2(14 downto 9)<=d9_out_bus(5 downto 0);

adb<=bus1(6);

da_out_bus<=bus1(2)&bus1(1);

rpz<=bus1(7);

vm_bus<=bus2(8 downto 1);

rpz_bus<=bus2(14 downto 9);

-- <<enter your statements here>>

end top;

Waveform схемы