port (
a: in STD_LOGIC_VECTOR (7 downto 0);
en_inv: in STD_LOGIC;
q: out STD_LOGIC_VECTOR (7 downto 0)
);
end k155re3_1;
architecture k155re3_1 of k155re3_1 is
begin
process (a,en_inv)
begin
if en_inv='0' then
case a is
when "00010000" => q<=transport "00000000" after 27ns;
when "00010001" => q<=transport "00000000" after 27ns;
when "00010010" => q<=transport "00000000" after 27ns;
when "00010011" => q<=transport "00000000" after 27ns;
when "00010100" => q<=transport "00000000" after 27ns;
when "00010101" => q<=transport "00000000" after 27ns;
when "00010110" => q<=transport "00000000" after 27ns;
when "00010111" => q<=transport "00000000" after 27ns;
when "00011000" => q<=transport "01111111" after 27ns;
when "00011001" => q<=transport "10111111" after 27ns;
when "00011010" => q<=transport "11011111" after 27ns;
when "00011011" => q<=transport "11101111" after 27ns;
when "00011100" => q<=transport "11110111" after 27ns;
when "00011101" => q<=transport "11111011" after 27ns;
when "00011110" => q<=transport "11111101" after 27ns;
when "00011111" => q<=transport "11111110" after 27ns;
when others => q<=transport "00000000" after 27ns;
end case;
end if;
end process;
-- <<enter your statements here>>
end k155re3_1;
k155re3.VHD
library IEEE;
use IEEE.std_logic_1164.all;
entity k155re3_2 is
port (
a: in STD_LOGIC_VECTOR (7 downto 0);
en_inv: in STD_LOGIC;
q: out STD_LOGIC_VECTOR (7 downto 0)
);
end k155re3_2;
architecture k155re3_2 of k155re3_2 is
begin
process (a,en_inv)
begin
if en_inv='0' then
case a is
when "00010000" => q<=transport "00000000" after 27ns;
when "00010001" => q<=transport "00000000" after 27ns;
when "00010010" => q<=transport "00000000" after 27ns;
when "00010011" => q<=transport "00000000" after 27ns;
when "00010100" => q<=transport "00000000" after 27ns;
when "00010101" => q<=transport "00000000" after 27ns;
when "00010110" => q<=transport "00000000" after 27ns;
when "00010111" => q<=transport "00000000" after 27ns;
when "00011000" => q<=transport "11111111" after 27ns;
when "00011001" => q<=transport "10000000" after 27ns;
when "00011010" => q<=transport "01000000" after 27ns;
when "00011011" => q<=transport "00100000" after 27ns;
when "00011100" => q<=transport "00010000" after 27ns;
when "00011101" => q<=transport "00001000" after 27ns;
when "00011110" => q<=transport "00000100" after 27ns;
when "00011111" => q<=transport "00000010" after 27ns;
when others => q<=transport "00000000" after 27ns;
end case;
end if;
end process;
-- <<enter your statements here>>
end k155re3_2;
k155tm7.VHD
library IEEE;
use IEEE.std_logic_1164.all;
entity k155tm7 is
port (
d1: in STD_LOGIC;
d2: in STD_LOGIC;
d3: in STD_LOGIC;
d4: in STD_LOGIC;
q1: out STD_LOGIC;
q2: out STD_LOGIC;
q3: out STD_LOGIC;
q4: out STD_LOGIC;
q1_inv: out STD_LOGIC;
q2_inv: out STD_LOGIC;
q3_inv: out STD_LOGIC;
q4_inv: out STD_LOGIC;
c1: in STD_LOGIC;
c2: in STD_LOGIC
);
end k155tm7;
architecture k155tm7 of k155tm7 is
begin
process (d1,d2,d3,d4,c1,c2)
variable d1_int,d2_int,d3_int,d4_int:STD_LOGIC;
begin
if c1='1' then
d1_int:=d1;
d2_int:=d2;
end if;
if c2='1' then
d3_int:=d3;
d4_int:=d4;
end if;
q1<=transport d1_int after 30ns;
q1_inv<=transport not d1_int after 30ns;
q2<=transport d2_int after 30ns;
q2_inv<=transport not d2_int after 30ns;
q3<=transport d3_int after 30ns;
q3_inv<=transport not d3_int after 30ns;
q4<=transport d4_int after 30ns;
q4_inv<=transport not d4_int after 30ns;
end process;
-- <<enter your statements here>>
end k155tm7;
k155la2.VHD
library IEEE;
use IEEE.std_logic_1164.all;
entity k155la2 is
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