Functional block diagram. Information furnished by Analog Devices is believed to be accurate. Guaranteed by design, but not production tested

a _{Complete DDS}CMOS

              FEATURES                                                                                                                         GENERAL DESCRIPTION

+5 V Pow er S upply                                                    This DDS device is a numerically controlled oscillator em50 MHz S peed                                                                      ploying a phase accumulator, a sine look-up table and a

On-C hip S INE L ook-Up Table 10-bit D/A converter integrated on a single CMOS chip. On-C hip 10-Bit DAC Modulation capabilities are provided for phase modulation

Parallel L oading                                                                                                            and frequency modulation.

^{Pow er-Dow n Option}                                                 Clock rates up to 50 MHz are supported.  Frequency accu^{72 dB S FDR}                                                                      racy can be controlled to one part in 4 billion. Modulation

^{250 m W Pow er C onsum ption}                              is effected by loading registers through the parallel micro48-Pin TQFP                                                                                                                    processor interface.

APPL IC ATIONS                                                          A power-down pin allows external control of a power-down

DDS Tuning                                                                              mode. The part is available in a 48-pin TQFP package.

Dig ital Dem odulation

FUNCTIONAL BLOCK DIAGRAM

REV. A

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AD9830–SPECIFICATIONS1 (V_DD = +5 V 6 5%; AGND = DGND = 0 V; T_A = T_MIN to T_MAX; REFIN = REFOUT;

R_SET = 1 kV; R_LOAD = 51 V for IOUT and IOUT unless otherwise noted