Моделирование электронных схем с применением САПР “Xilinx” на языке VHDL

Министерство Образования и Науки Российской Федерации

Красноярский Государственный Технический Университет

                                                                                            Кафедра: Радиотехники

Лабораторная работа № 3.

Моделирование электронных схем с применением САПР “Xilinx” на языке VHDL.

                                                                                       Выполнил: ст. гр. Р41-1

                                                                       Васильев И.В.

                                                                Проверил:

                                                                                          Кондратьев А. С.

Красноярск 2004

Цель работы:

Изучение возможностей программы “Xilinx” для моделирования электронных схем с применением поведенческого описания схем на языке VHDL.

В лабораторной работе моделируется решающее устройство импульсной РЛС, работающей по 4 частотным каналам. При этом решение о наличии цели принимается по критерию 5 из 7 по каждому частотному каналу и для выхода всего устройства по критерию 3 из 4.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

Модульный файл (VHDL Module)

entity vvv is

    Port ( TEST_1 : in std_logic;

           REF_1 : in std_logic;

           REF_2 : in std_logic;

           TEST_2 : in std_logic;

           REF_3 : in std_logic;

           REF_4 : in std_logic;

           CLK_1 : in std_logic;

           RESET_1 : in std_logic;

           DC_1_ENABLE : in std_logic;

           S_0 : in std_logic;

           S_1 : in std_logic;

           CLK_2 : in std_logic;

           RESET_2 : in std_logic;

           DC_2_ENABLE : in std_logic;

           TARGET : out std_logic;

                         outxnor_1 : out std_logic;

                         outxnor_2 : out std_logic;

                         outxnor_3 : out std_logic;

                         outxnor_4 : out std_logic;

                         outcounter_11 : out std_logic_vector (3 downto 0);

                         outcounter_12 : out std_logic_vector (3 downto 0);

                         outcounter_13 : out std_logic_vector (3 downto 0);

                         outcounter_14 : out std_logic_vector (3 downto 0);

                         outdc_11 : out std_logic_vector (15 downto 0);

                         outdc_12 : out std_logic_vector (15 downto 0);

                         outdc_13 : out std_logic_vector (15 downto 0);

                         outdc_14 : out std_logic_vector (15 downto 0);

                         outor_11 : out std_logic_vector (3 downto 0);

                         outmux_11 : out std_logic;

                         outcounter_21 : out std_logic_vector (3 downto 0);

                         outdc_21 : out std_logic_vector (15 downto 0)

                         );

end vvv;

architecture Behavioral of vvv is

signal outxnor : std_logic_vector (3 downto 0);

signal outcounter_1 : std_logic_vector (3 downto 0);

signal outcounter_2 : std_logic_vector (3 downto 0);

signal outcounter_3 : std_logic_vector (3 downto 0);

signal outcounter_4 : std_logic_vector (3 downto 0);

signal outdc_1 : std_logic_vector (15 downto 0);

signal outdc_2 : std_logic_vector (15 downto 0);

signal outdc_3 : std_logic_vector (15 downto 0);

signal outdc_4 : std_logic_vector (15 downto 0);

signal outor_1 : std_logic_vector (3 downto 0);

signal outmux : std_logic;

signal outcounter : std_logic_vector (3 downto 0);

signal outdc : std_logic_vector (15 downto 0);

signal outor : std_logic;

begin

process ( TEST_1, TEST_2, REF_1, REF_2, REF_3, REF_4)

begin

outxnor(0) <= TEST_1 xnor REF_1;

outxnor(1) <= TEST_1 xnor REF_2;

outxnor(2) <= TEST_2 xnor REF_3;

outxnor(3) <= TEST_2 xnor REF_4;

end process;

process (CLK_1, RESET_1, outxnor (0))

variable COUNT : std_logic_vector (3 downto 0);

begin

if RESET_1 = '1' then

COUNT := "0000";

elsif CLK_1'EVENT and CLK_1 = '1' and outxnor(0) = '1' then

COUNT := COUNT + "0001";

end if;

outcounter_1 <= COUNT;

end process;

process (CLK_1, RESET_1, outxnor (1))

variable COUNT : std_logic_vector (3 downto 0);

begin

if RESET_1 = '1' then

COUNT := "0000";

elsif CLK_1'EVENT and CLK_1 = '1' and outxnor(1) = '1' then

COUNT := COUNT + "0001";

end if;

outcounter_2 <= COUNT;

end process;

process (CLK_1, RESET_1, outxnor (2))

variable COUNT : std_logic_vector (3 downto 0);

begin

if RESET_1 = '1' then

COUNT := "0000";

elsif CLK_1'EVENT and CLK_1 = '1' and outxnor(2) = '1' then

COUNT := COUNT + "0001";

end if;

outcounter_3 <= COUNT;

end process;

process (CLK_1, RESET_1, outxnor (3))

variable COUNT : std_logic_vector (3 downto 0);

begin

if RESET_1 = '1' then

COUNT := "0000";

elsif CLK_1'EVENT and CLK_1 = '1' and outxnor(3) = '1' then

COUNT := COUNT + "0001";

end if;

outcounter_4 <= COUNT;

end process;

process (DC_1_ENABLE, outcounter_1)

begin

if DC_1_ENABLE = '0' then

outdc_1 <= "0000000000000000";

else

            case outcounter_1 is

            when "0000"   => outdc_1 <= "0000000000000001";

            when "0001"   => outdc_1 <= "0000000000000010";

            when "0010"   => outdc_1 <= "0000000000000100";

            when "0011"   => outdc_1 <= "0000000000001000";

            when "0100"   => outdc_1 <= "0000000000010000";

            when "0101"   => outdc_1 <= "0000000000100000";

            when "0110"   => outdc_1 <= "0000000001000000";

            when "0111"   => outdc_1 <= "0000000010000000";

            when "1000"   => outdc_1 <= "0000000100000000";

            when "1001"   => outdc_1 <= "0000001000000000";

            when "1010"   => outdc_1 <= "0000010000000000";

            when "1011"   => outdc_1 <= "0000100000000000";

            when "1100"   => outdc_1 <= "0001000000000000";

            when "1101"   => outdc_1 <= "0010000000000000";

            when "1110"   => outdc_1 <= "0100000000000000";

            when "1111"   => outdc_1 <= "1000000000000000";

            when others => outdc_1 <= "0000000000000000";

            end case;

end if;

end process;

process (DC_1_ENABLE, outcounter_2)

begin

if DC_1_ENABLE = '0' then

outdc_2 <= "0000000000000000";

else

            case outcounter_2 is

            when "0000"   => outdc_2 <= "0000000000000001";

            when "0001"   => outdc_2 <= "0000000000000010";

            when "0010"   => outdc_2 <= "0000000000000100";

            when "0011"   => outdc_2 <= "0000000000001000";

            when "0100"   => outdc_2 <= "0000000000010000";

            when "0101"   => outdc_2 <= "0000000000100000";

            when "0110"   => outdc_2 <= "0000000001000000";