Устройство ввода многоканальной информации в микроЭВМ "Электроника 60". Описание работы компонентов схемы, страница 5

<<enter your statements here>>

process(k1,k2)

begin

T<= k1 or k2 after 10 ns;

end process;

end K559ip2;

Модель элемента К589АП26

---  File: K589AP26.vhd

--  created by Design Wizard: 05/16/02 16:46:58

-library IEEE;

use IEEE.std_logic_1164.all;

entity K589AP26 is

port (

DCE: in STD_LOGIC;

CS: in STD_LOGIC;

DI0:      inout      STD_LOGIC;

DI1:      inout      STD_LOGIC;

DI2:      inout      STD_LOGIC;

DI3:      inout      STD_LOGIC;

DB0:     inout      STD_LOGIC;

DB1:     inout      STD_LOGIC;

DB2:     inout      STD_LOGIC;

DB3:     inout      STD_LOGIC;

D00:     inout      STD_LOGIC;

D01:     inout      STD_LOGIC;

D02:     inout      STD_LOGIC;

D03:     inout      STD_LOGIC

);

end K589AP26;

architecture K589AP26 of K589AP26 is

begin

-- <<enter your statements here>> Process(DCE,CS,DI0,DI1,DI2,DI3,DB0,DB1,DB2,DB3,D00,D01,D02,D03) begin

if DCE='0' and CS='0' then

DB0<=DI0 after 25 ns;

DB1<=DI1 after 25 ns;

DB2<=DI2 after 25 ns;

DB3<=DI3 after 25 ns; end if;

if DCE='1' and CS='0' then

D00<=DB0 after 25 ns;

D01<=DB1 after 25 ns;

D02<=DB2 after 25 ns;

D03<=DB3 after 25 ns; end if;

if DCE='1' and CS='1' then

D00<='Z' after 25 ns;

D01<='Z' after 25 ns;

D02<='Z' after 25 ns;

D03<='Z' after 25 ns; end if;

end process;

end K589AP26;

Модель элемента К599ИП1

---  File: K599ip1.vhd

--  created by Design Wizard: 05/16/02 18:01:21

-library IEEE;

use IEEE.std_logic_1164.all;

entity K599ip1 is

port (

F1: in STD_LOGIC;

F2: in STD_LOGIC;

L1: out STD_LOGIC

);

end K599ip1;

architecture K599ip1 of K599ip1 is

begin

-- <<enter your statements here>>

process (F1,F2)

begin

L1<=F1 and F2 after 10ns;

end process;

end K599ip1;

3.2 Моделирование схемы.

library IEEE;

use IEEE.std_logic_1164.all;

entity Uenter is

port (k1: in STD_LOGIC;

k2:    in STD_LOGIC;

k3:    in STD_LOGIC;

k4:    in STD_LOGIC;

k5:    in STD_LOGIC;

k6:    inout STD_LOGIC;

k7:    inout STD_LOGIC;

k8:    inout STD_LOGIC;

k9:    inout STD_LOGIC;

k10:     inout      STD_LOGIC;

k11:     inout      STD_LOGIC;

k12:     inout      STD_LOGIC;

k13:     inout      STD_LOGIC;

k14:     inout      STD_LOGIC;

k15:     inout      STD_LOGIC;

k16:     inout      STD_LOGIC;

k17:     inout      STD_LOGIC;

sg59,sg60,sg61,sg62,sg67,sg68,sg69,sg70,sg74,sg75,sg76,sg77:in std_logic;

--    OUT

z1:     out    STD_LOGIC;

z2:     out    STD_LOGIC;

z3:     out    STD_LOGIC;

z4:     out    STD_LOGIC;

z5:     out    STD_LOGIC;

z6:     out    STD_LOGIC;

z7:     out    STD_LOGIC;

z8:     out    STD_LOGIC;

z9:     out    STD_LOGIC;

z10:     out    STD_LOGIC;

z11:     out    STD_LOGIC;

z12:     out    STD_LOGIC;

z13:     out    STD_LOGIC;

z14:     out    STD_LOGIC

);

end Uenter;

architecture Structure of Uenter is

component K559ip2 is

port (

k1: in STD_LOGIC;

k2: in STD_LOGIC;

T: out STD_LOGIC

);

end component;

component K599ip1 is

port (  F1: in STD_LOGIC;

F2: in STD_LOGIC;

L1: out STD_LOGIC

);

end component;

component K589AP26 is

port (  DCE: in STD_LOGIC;

CS: in STD_LOGIC;

--                 DI0: inout STD_LOGIC;

--                 DI1: inout STD_LOGIC;

--                 DI2: inout STD_LOGIC;

--                 DI3: inout STD_LOGIC;

DB0:     inout STD_LOGIC;

DB1:     inout STD_LOGIC;

DB2:     inout STD_LOGIC;

DB3:     inout STD_LOGIC;

D00:     out STD_LOGIC;

D01:     out STD_LOGIC;

D02:     out STD_LOGIC;

D03:     out STD_LOGIC

);

end component;

component K155la2 is

port (  x1: inout STD_LOGIC;

x2:    inout      STD_LOGIC;

x3:    inout      STD_LOGIC;

x4:    inout      STD_LOGIC;

x5:    inout      STD_LOGIC;

x6:    inout      STD_LOGIC;

x7:    inout      STD_LOGIC;

x8:    inout      STD_LOGIC;

y1: out STD_LOGIC

);

end component;

component K155ru2 is

port (  aa1: in STD_LOGIC;

aa2: in STD_LOGIC;

aa3: in STD_LOGIC;

aa4: in STD_LOGIC;

cs: in STD_LOGIC;

w: in STD_LOGIC;

dd1:     in STD_LOGIC;

dd2:     in STD_LOGIC;

dd3:     in STD_LOGIC;

dd4:     in STD_LOGIC;

qq1:     out STD_LOGIC;

qq2:     out STD_LOGIC;

qq3:     out STD_LOGIC;