Устройство ввода многоканальной информации в микроЭВМ "Электроника 60". Описание работы компонентов схемы, страница 4

Модель элемента К155ЛЕ1

---  File: K155Le1.vhd

--  created by Design Wizard: 05/13/02 20:43:31

-library IEEE;

use IEEE.std_logic_1164.all;

entity K155Le1 is

port (

d1: inout STD_LOGIC;

d2: inout STD_LOGIC;

q2: out STD_LOGIC

);

end K155Le1;

architecture K155Le1 of K155Le1 is

begin

-- <<enter your statements here>>

Process (d1,d2)

Begin

q2<=not (d1 or d2)after 15 ns;

End process;

end K155Le1;

Модель элемента К155РУ2

---  File: K155--2.vhd

--  created by Design Wizard: 05/14/02 10:26:47

-library IEEE;

use IEEE.std_logic_1164.all;

entity K155RU2 is

port (

aa1: in STD_LOGIC;

aa2: in STD_LOGIC;

aa3: in STD_LOGIC;

aa4: in STD_LOGIC;

cs: in STD_LOGIC;

w: in STD_LOGIC;

dd1:       in STD_LOGIC;

dd2:       in STD_LOGIC;

dd3:       in STD_LOGIC;

dd4:       in STD_LOGIC;

qq1:       out STD_LOGIC;

qq2:       out STD_LOGIC;

qq3:       out STD_LOGIC;

qq4:       out STD_LOGIC

);

end K155RU2;

architecture K155RU2 of K155RU2 is

begin

-- <<enter your statements here>>

Process (aa1,aa2,aa3,aa4,cs,w,dd1,dd2,dd3,dd4) type tab is array (0 to 15, 1 to 4) of std_logic; variable chislo : integer;

variable mas : tab;

variable aaa1,aaa2,aaa3,aaa4 : Integer;

begin

aaa1:=0; aaa2:=0; aaa3:=0; aaa4:=0;

if aa1='1' then aaa1:=1; End if;

if aa2='1' then aaa2:=1; End if;

if aa3='1' then aaa3:=1; End if;

if aa4='1' then aaa4:=1; End if; chislo:=1*aaa1+2*aaa2+4*aaa3+8*aaa4; if cs='0' and w='0' Then

mas(chislo,1):=dd1;

mas(chislo,2):=dd2;

mas(chislo,3):=dd3;

mas(chislo,4):=dd4;

end if;

If w='1' and cs='0' Then

qq1<= not mas(chislo,1)after 50 ns;

qq2<= not mas(chislo,2)after 50 ns;

qq3<= not mas(chislo,3) after 50 ns;

qq4<= not mas(chislo,4) after 50 ns; end if;

end process;

end K155RU2;

Модель элемента К155ТМ8

---  File: K155TM8.vhd

--  created by Design Wizard: 03/19/02 23:19:58

-library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_unsigned.all;

entity K155TM8 is

port (

RESET: in STD_LOGIC;

CLK: in STD_LOGIC;

D5_0: in STD_LOGIC;

D5_1: in STD_LOGIC;

D5_2: in STD_LOGIC;

D5_3: in STD_LOGIC;

Q5_N0: out STD_LOGIC;

Q5_0: out STD_LOGIC;

Q5_N1: out STD_LOGIC;

Q5_1: out STD_LOGIC;

Q5_N2: out STD_LOGIC;

Q5_2: out STD_LOGIC;

Q5_N3: out STD_LOGIC;

Q5_3: out STD_LOGIC

);

end K155TM8;

architecture K155TM8 of K155TM8 is

begin

process (CLK,RESET,D5_0,D5_1,D5_2,D5_3) variable q51,q50,q52,q53:std_logic;

begin

if RESET='0' then

q50 := '0';

q51 := '0';

q52 := '0';

q53 := '0';

else

if CLK' event  and CLK='1' then

q50 := D5_0;

q51 := D5_1;

q52 := D5_2;

q53 := D5_3;

end if;

end if;

Q5_0 <= q50             after 35 ns;

Q5_1 <= q51             after 35 ns;

Q5_2 <= q52             after 35 ns;

Q5_3 <= q53             after 35 ns;

Q5_N0 <=not            q50 after 35 ns;

Q5_N1 <=not            q51 after 35 ns;

Q5_N2 <=not            q52 after 35 ns;

Q5_N3 <=not            q53 after 35 ns;

end process;

end K155TM8;

Модель элемента К155ТМ2

---  File: K155TM2.vhd

--  created by Design Wizard: 05/15/02 10:52:21

-library IEEE;

use IEEE.std_logic_1164.all;

entity K155TM2 is

port (

R_1:        in STD_LOGIC;

C_1:        in STD_LOGIC;

D_1:        in STD_LOGIC;

S_1:        in STD_LOGIC;

Q_1:        out STD_LOGIC;

Q_N_1: out STD_LOGIC

);

end K155TM2;

architecture K155TM2 of K155TM2 is

begin

Process(R_1,C_1,S_1,D_1)

Begin

If S_1='0' and R_1='1' Then

Q_1 <='1'  after 35 ns;

Q_N_1 <='0' after 35 ns; End if;

If s_1='1' and R_1='0' Then Q_1 <='0'  after 35 ns; Q_N_1 <='1'  after 35 ns;

End if;

If s_1='0' and R_1='0' Then Q_1 <='1'  after 35 ns; Q_N_1 <='1'  after 35 ns;

End if;

If c_1' event and c_1='1' and s_1='1' and R_1='1' Then Q_1 <=D_1  after 35 ns;

Q_N_1 <=not D_1 after 35 ns;

End if;

End process; еnd K155TM2;

Модель элемента К559ИП2

---  File: K559ip2.vhd

--  created by Design Wizard: 05/16/02 17:52:22

-library IEEE;

use IEEE.std_logic_1164.all;

entity K559ip2 is

port (

k1: in STD_LOGIC;

k2: in STD_LOGIC;

T: out STD_LOGIC

);

end K559ip2;

architecture K559ip2 of K559ip2 is

begin